公开(公告)号：US08141379B2

公开(公告)日：2012-03-27

申请号：US12959110

申请日：2010-12-02

申请人： Luai M. Al-Hadhrami ,  Aftab Ahmad ,  Shafiqur Rehman

发明人： Luai M. Al-Hadhrami ,  Aftab Ahmad ,  Shafiqur Rehman

IPC分类号： F25D23/00

CPC分类号： F24F3/1417 ,  F24F5/0035 ,  F24F2001/0092 ,  F24F2005/0064 ,  F24S21/00 ,  Y02B30/545 ,  Y02E10/40

摘要： The hybrid solar air-conditioning system includes an air intake having an air drying system that uses a liquid desiccant to dry ambient air, a desiccant regeneration system that uses a heat exchanger having oil heated by solar energy to remove water from the desiccant, an indirect evaporative air conditioner that uses an air-air heat exchanger to cool the dried air indirectly with evaporatively cooled air, a distilled water recovery system to recover water from the desiccant and from the evaporatively cooled air in the form of distilled water, and a microprocessor-based controller to control room temperature and relative humidity, and to regulate air intake and the flow of desiccant and oil in the system. The hybrid system enables the use of evaporative cooling in regions having high humidity.

摘要翻译： 混合式太阳能空调系统包括具有使用液体干燥剂干燥环境空气的空气干燥系统的进气口，使用具有由太阳能加热的油从而从干燥剂中除去水的热交换器的干燥剂再生系统， 蒸发式空气调节器，其使用空气热交换器间接地用蒸发冷却的空气冷却干燥空气;蒸馏水回收系统，用于从干燥剂和蒸馏水形式的蒸发冷却空气中回收水;以及微处理器 - 控制室内温度和相对湿度，并调节系统中的空气摄入量和干燥剂和油的流量。 混合系统能够在具有高湿度的区域中使用蒸发冷却。

公开(公告)号：US08869627B2

公开(公告)日：2014-10-28

申请号：US13544671

申请日：2012-07-09

申请人： Luai M. Al-Hadhrami ,  Shafiqur Rehman ,  Aftab Ahmad

发明人： Luai M. Al-Hadhrami ,  Shafiqur Rehman ,  Aftab Ahmad

IPC分类号： G01F1/74

CPC分类号： G01F1/74 ,  G01F15/08

摘要： The multi-phase flow metering system facilitates the measurement of the flow of oil, gas, and/or other materials from one or more producing petroleum wells. The system has an expansion chamber to separate liquid and as phases. The gas rises through a pipe extending from the top of the expansion chamber. Liquids flow from the bottom of the expansion chamber through a generally U-shaped line having a sediment trap therein. Separate metering devices are provided in the gas outflow line and in the liquid line for accurately measuring the flow of each phase, and in the inlet line for measuring temperature, pressure, and flow at that point. The system includes float valves at the inlet to the gas outflow line and at the liquid phase outlet to control flow through the system. The gas outflow line may continue as a separate line, or reconnect to the liquid outflow line.

摘要翻译： 多相流量计量系统有助于测量来自一个或多个生产石油井的油，气和/或其它材料的流动。 该系统具有用于分离液体和分相的膨胀室。 气体通过从膨胀室的顶部延伸的管道上升。 液体从膨胀室的底部流过其中具有沉淀物捕集器的大致U形的管线。 在气体流出管线和液体管线中设置有单独的计量装置，用于精确地测量每个相的流量，以及在该点处测量温度，压力和流量的入口管线。 该系统包括在气体流出管线和液相出口的入口处的浮阀，以控制通过系统的流量。 气体流出管线可以作为单独的管线继续，或者重新连接到液体流出管线。

公开(公告)号：US07176549B2

公开(公告)日：2007-02-13

申请号：US11012012

申请日：2004-12-13

申请人： Klaus F. Schuegraf ,  Aftab Ahmad

发明人： Klaus F. Schuegraf ,  Aftab Ahmad

IPC分类号： H01L29/00

CPC分类号： H01L21/76224 ,  Y10S148/05

摘要： A shallow trench isolation is disclosed wherein the trench depth is reduced beyond that achieved in prior art processes. The reduced trench depth helps to eliminate the formation of voids during the trench refill process and provides for greater planarity in the final isolation structure. Effective device isolation is achieved with a reduced trench depth by utilizing refilling dielectric materials having low dielectric constant.

摘要翻译： 公开了一种浅沟槽隔离，其中沟槽深度减小到超过现有技术工艺中所达到的深度。 减小的沟槽深度有助于在沟槽再填充过程期间消除空隙的形成，并且在最终隔离结构中提供更大的平坦度。 通过利用具有低介电常数的再填充介电材料，通过减小沟槽深度实现有效的器件隔离。

公开(公告)号：US06930363B2

公开(公告)日：2005-08-16

申请号：US10901552

申请日：2004-07-27

申请人： Nanseng Jeng ,  Aftab Ahmad

发明人： Nanseng Jeng ,  Aftab Ahmad

IPC分类号： H01L21/28 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/94

CPC分类号： H01L29/4941 ,  H01L21/28061 ,  H01L21/823437

摘要： A barrier layer comprising silicon mixed with an impurity is disclosed for protection of gate dielectrics in integrated transistors. In particular, the barrier layer comprises silicon incorporating nitrogen. The nitrogen can be incorporated into an upper portion of the gate polysilicon during deposition, or a silicon layer doped with nitrogen after silicon deposition. The layer is of particular utility in conjunction with CVD tungsten silicide straps.

摘要翻译： 公开了包含与杂质混合的硅的阻挡层，用于保护集成晶体管中的栅极电介质。 特别地，阻挡层包括掺入氮的硅。 在沉积期间可以将氮结合到栅极多晶硅的上部，或在硅沉积之后掺入氮的硅层。 该层与CVD钨硅化物带结合是特别实用的。

公开(公告)号：US06770571B2

公开(公告)日：2004-08-03

申请号：US10339731

申请日：2003-01-08

申请人： Nanseng Jeng ,  Aftab Ahmad

发明人： Nanseng Jeng ,  Aftab Ahmad

IPC分类号： H01L2131

CPC分类号： H01L29/4941 ,  H01L21/28061 ,  H01L21/823437

摘要： A barrier layer comprising silicon mixed with an impurity is disclosed for protection of gate dielectrics in integrated transistors. In particular, the barrier layer comprises silicon incorporating nitrogen. The nitrogen can be incorporated into an upper portion of the gate polysilicon during deposition, or a silicon layer doped with nitrogen after silicon deposition. The layer is of particular utility in conjunction with CVD tungsten silicide straps.

摘要翻译： 公开了包含与杂质混合的硅的阻挡层，用于保护集成晶体管中的栅极电介质。 特别地，阻挡层包括掺入氮的硅。 在沉积期间可以将氮结合到栅极多晶硅的上部，或在硅沉积之后掺入氮的硅层。 该层与CVD钨硅化物带结合是特别实用的。

公开(公告)号：US06743979B1

公开(公告)日：2004-06-01

申请号：US10652453

申请日：2003-08-29

申请人： Michael J. Berman ,  Aftab Ahmad ,  Qwai H. Low ,  Chok J. Chia ,  Ramaswamy Ranganathan

发明人： Michael J. Berman ,  Aftab Ahmad ,  Qwai H. Low ,  Chok J. Chia ,  Ramaswamy Ranganathan

IPC分类号： H05K506

CPC分类号： H01L24/06 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/49431 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012

摘要： An integrated circuit, including a substrate with circuitry formed therein, where the substrate has a peripheral edge. Also included are a top most electrically conductive layer and an underlying electrically conductive layer. Outer bonding pads are disposed in an outer ring, and are formed within the top most layer. Inner bonding pads are disposed in an inner ring, and are formed within the top most layer. Inner connectors electrically connect the inner bonding pads to the circuitry. The inner connectors are formed within the underlying layer, and have a width that is less than the width of the inner bonding pads, thereby defining a gap between the inner connectors. Outer connectors electrically connect the outer bonding pads to the circuitry. The outer connectors are formed within the underlying layer, and have a width that is less than the width of the gap between the inner connectors.

摘要翻译： 一种集成电路，包括其中形成有电路的衬底，其中衬底具有外围边缘。 还包括最顶层的导电层和底层导电层。 外部接合焊盘设置在外圈中，并形成在最上层。 内部接合焊盘设置在内圈中，并且形成在最顶层内。 内部连接器将内部接合焊盘电连接到电路。 内部连接器形成在下面的层中，并且具有小于内部焊盘的宽度的宽度，由此限定内部连接器之间的间隙。 外部连接器将外部接合焊盘电连接到电路。 外部连接器形成在下面的层中，并且具有小于内部连接器之间的间隙的宽度的宽度。

公开(公告)号：US06373114B1

公开(公告)日：2002-04-16

申请号：US09178306

申请日：1998-10-23

申请人： Nanseng Jeng ,  Aftab Ahmad

发明人： Nanseng Jeng ,  Aftab Ahmad

IPC分类号： H01L2994

CPC分类号： H01L29/4941 ,  H01L21/28061 ,  H01L21/823437

摘要： A barrier layer comprising silicon mixed with an impurity is disclosed for protection of gate dielectrics in integrated transistors. In particular, the barrier layer comprises silicon incorporating nitrogen. The nitrogen can be incorporated into an upper portion of the gate polysilicon during deposition, or a silicon layer doped with nitrogen after silicon deposition. The layer is of particular utility in conjunction with CVD tungsten silicide straps.

摘要翻译： 公开了包含与杂质混合的硅的阻挡层，用于保护集成晶体管中的栅极电介质。 特别地，阻挡层包括掺入氮的硅。 在沉积期间可以将氮结合到栅极多晶硅的上部，或在硅沉积之后掺入氮的硅层。 该层与CVD钨硅化物带结合是特别实用的。

公开(公告)号：US06281092B1

公开(公告)日：2001-08-28

申请号：US09347487

申请日：1999-07-02

申请人： Aftab Ahmad

发明人： Aftab Ahmad

IPC分类号： H01L218242

CPC分类号： H01L28/91 ,  H01L21/3212

摘要： A capacitor is fabricated on a semiconductor substrate by first forming a first capacitor electrode on the semiconductor substrate and forming a planar insulating layer over the first capacitor electrode. A photoresist layer is then formed over the planar insulating layer and patterned utilizing in only masking step to form an opening over the first capacitor electrode. Through the opening, the planar insulating layer is etched, and a capacitor dielectric layer is thereafter formed. A second capacitor electrode is then formed over the capacitor dielectric layer in alignment with the first capacitor electrode. The structure is planarized to expose the planar insulating layer. In a preferred embodiment, a trench in the second capacitor electrode is protected during planarization by a spin-on photoresist that is stripped following planarization.

摘要翻译： 在半导体衬底上制造电容器，首先在半导体衬底上形成第一电容器电极，并在第一电容器电极上形成平面绝缘层。 然后在平面绝缘层上形成光致抗蚀剂层，并且仅在掩模步骤中利用图案化以在第一电容器电极上形成开口。 通过开口蚀刻平面绝缘层，然后形成电容器电介质层。 然后在电容器电介质层上形成与第一电容器电极对准的第二电容器电极。 将该结构平坦化以暴露平面绝缘层。 在优选实施例中，第二电容器电极中的沟槽在平坦化期间通过在平坦化之后剥离的旋涂光致抗蚀剂被保护。

公开(公告)号：US6046472A

公开(公告)日：2000-04-04

申请号：US949997

申请日：1997-10-14

申请人： Aftab Ahmad ,  Charles Dennison

发明人： Aftab Ahmad ,  Charles Dennison

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78 ,  H01L29/784

CPC分类号： H01L29/6659 ,  H01L21/28247 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/7833 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S257/917

摘要： A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N- LDD regions and N+ source and drain electrodes. The phosphorous implant is driven to diffuse across both the electrode/LDD junctions and the LDD/channel junctions.

公开(公告)号：US5946588A

公开(公告)日：1999-08-31

申请号：US779602

申请日：1997-01-07

申请人： Aftab Ahmad ,  Randhir P. S. Thakur ,  J. Brett Rolfson ,  Brian Benard

发明人： Aftab Ahmad ,  Randhir P. S. Thakur ,  J. Brett Rolfson ,  Brian Benard

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/762

CPC分类号： H01L21/28211 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/76216

摘要： A process for making thin gate oxides comprising the layering of a semiconductor substrate with at least an oxide layer and a nitride layer. The layers are then patterned and etched, thereby exposing portions of the substrate. The substrate is then doped, thereby creating a channel stop region. The exposed portions of the substrate are oxidized, thereby creating a field oxide region. The oxide and nitride layers are removed, thereby exposing sites of active areas, and a gate oxide layer grown in an ozone-containing atmosphere.

摘要翻译： 一种用于制造薄栅极氧化物的方法，包括至少具有氧化物层和氮化物层的半导体衬底的层叠。 然后对这些层进行图案化和蚀刻，从而暴露衬底的部分。 然后将衬底掺杂，从而形成通道停止区域。 衬底的暴露部分被氧化，从而产生场氧化物区域。 去除氧化物和氮化物层，从而暴露有源区的位置，以及在含臭氧的气氛中生长的栅极氧化物层。