公开(公告)号：US08023345B2

公开(公告)日：2011-09-20

申请号：US12391693

申请日：2009-02-24

申请人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Stefanie R. Chiras ,  Ibrahim M. Elfadel ,  Michele M. Franceschini ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Thomas Mittelholzer ,  Mayank Sharma

发明人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Stefanie R. Chiras ,  Ibrahim M. Elfadel ,  Michele M. Franceschini ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Thomas Mittelholzer ,  Mayank Sharma

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/02 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C29/021 ,  G11C29/028 ,  G11C2013/0092

摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.

摘要翻译： 提供了用于向内存位置迭代地写入内容的系统，方法和设备。 统计模型用于确定将所需内容写入存储器位置的脉冲序列。 内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。 对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。 读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。 统计模型和查询表可用于选择和修改脉冲。 自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

公开(公告)号：US08897062B2

公开(公告)日：2014-11-25

申请号：US13150690

申请日：2011-06-01

申请人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Stefanie R. Chiras ,  Ibrahim M. Elfadel ,  Michele M. Franceschini ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Thomas Mittelholzer ,  Mayank Sharma

发明人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Stefanie R. Chiras ,  Ibrahim M. Elfadel ,  Michele M. Franceschini ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Thomas Mittelholzer ,  Mayank Sharma

IPC分类号： G11C11/00 ,  G11C13/00 ,  G11C29/02

CPC分类号： G11C29/02 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C29/021 ,  G11C29/028 ,  G11C2013/0092

摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.

摘要翻译： 提供了用于向内存位置迭代地写入内容的系统，方法和设备。 统计模型用于确定将所需内容写入存储器位置的脉冲序列。 内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。 对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。 读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。 统计模型和查询表可用于选择和修改脉冲。 自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

公开(公告)号：US20110228600A1

公开(公告)日：2011-09-22

申请号：US13150690

申请日：2011-06-01

申请人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Stefanie R. Chiras ,  Ibrahim M. Elfadel ,  Michele M. Franceschini ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Thomas Mittelholzer ,  Mayank Sharma

发明人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Stefanie R. Chiras ,  Ibrahim M. Elfadel ,  Michele M. Franceschini ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Thomas Mittelholzer ,  Mayank Sharma

IPC分类号： G11C11/21

CPC分类号： G11C29/02 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C29/021 ,  G11C29/028 ,  G11C2013/0092

摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.

摘要翻译： 提供了用于向内存位置迭代地写入内容的系统，方法和设备。 统计模型用于确定将所需内容写入存储器位置的脉冲序列。 内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。 对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。 读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。 统计模型和查询表可用于选择和修改脉冲。 自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

公开(公告)号：US20100214829A1

公开(公告)日：2010-08-26

申请号：US12391693

申请日：2009-02-24

申请人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Stefanie R. Chiras ,  Ibrahim M. Elfadel ,  Michele M. Franceschini ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Thomas Mittelholzer ,  Mayank Sharma

发明人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Stefanie R. Chiras ,  Ibrahim M. Elfadel ,  Michele M. Franceschini ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Thomas Mittelholzer ,  Mayank Sharma

IPC分类号： G11C11/00

CPC分类号： G11C29/02 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C29/021 ,  G11C29/028 ,  G11C2013/0092

摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.

摘要翻译： 提供了用于向内存位置迭代地写入内容的系统，方法和设备。 统计模型用于确定将所需内容写入存储器位置的脉冲序列。 内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。 对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。 读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。 统计模型和查询表可用于选择和修改脉冲。 自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

公开(公告)号：US08166368B2

公开(公告)日：2012-04-24

申请号：US12391678

申请日：2009-02-24

申请人： Luis A. Lastras-Montano ,  John P. Karidis ,  Stefanie R. Chiras ,  Mayank Sharma ,  Thomas Mittelholzer ,  Michele M. Franceschini

发明人： Luis A. Lastras-Montano ,  John P. Karidis ,  Stefanie R. Chiras ,  Mayank Sharma ,  Thomas Mittelholzer ,  Michele M. Franceschini

IPC分类号： G06F11/00

CPC分类号： G06F11/1008 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/154

摘要： A method for writing in a memory system that includes receiving an address corresponding to a memory location in a memory, receiving a desired content to be written, encoding the desired content into a symbol, and writing the symbol to the memory location using an iterative write process of at least one write and one read to the memory location. The iterative write process includes determining if the symbol was successfully written to the memory location and exiting the iterative write process in response to the symbol being successfully written to the memory location. The iterative write process also includes determining if a halt condition has been met and exiting the iterative write process if the halt condition has been met. Once the iterative write process has been exited, the memory location may be identified as a candidate for being written with a special symbol.

摘要翻译： 一种用于在存储器系统中写入的方法，包括接收与存储器中的存储器位置相对应的地址，接收要写入的期望内容，将期望内容编码为符号，以及使用迭代写入将符号写入存储器位置 处理至少一次写入和一次读取到存储器位置。 迭代写入过程包括确定符号是否成功写入存储器位置，并响应于被成功写入存储器位置的符号退出迭代写入过程。 迭代写入过程还包括如果已经满足停止条件，则确定是否满足了停止条件并退出迭代写入过程。 一旦迭代写入过程已被退出，存储器位置可以被识别为用特殊符号写入的候选。

公开(公告)号：US20100218071A1

公开(公告)日：2010-08-26

申请号：US12391678

申请日：2009-02-24

申请人： Luis A. Lastras-Montano ,  John P. Karidis ,  Stefanie R. Chiras ,  Mayank Sharma ,  Thomas Mittelholzer ,  Michele M. Franceschini

发明人： Luis A. Lastras-Montano ,  John P. Karidis ,  Stefanie R. Chiras ,  Mayank Sharma ,  Thomas Mittelholzer ,  Michele M. Franceschini

IPC分类号： G06F12/00 ,  H03M13/05 ,  G06F11/10

CPC分类号： G06F11/1008 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/154

摘要： A method for writing in a memory system that includes receiving an address corresponding to a memory location in a memory, receiving a desired content to be written, encoding the desired content into a symbol, and writing the symbol to the memory location using an iterative write process of at least one write and one read to the memory location. The iterative write process includes determining if the symbol was successfully written to the memory location and exiting the iterative write process in response to the symbol being successfully written to the memory location. The iterative write process also includes determining if a halt condition has been met and exiting the iterative write process if the halt condition has been met. Once the iterative write process has been exited, the memory location may be identified as a candidate for being written with a special symbol.

摘要翻译： 一种用于在存储器系统中写入的方法，包括接收与存储器中的存储器位置相对应的地址，接收要写入的期望内容，将期望内容编码为符号，以及使用迭代写入将符号写入存储器位置 处理至少一次写入和一次读取到存储器位置。 迭代写入过程包括确定符号是否成功写入存储器位置，并响应于被成功写入存储器位置的符号退出迭代写入过程。 迭代写入过程还包括如果已经满足停止条件，则确定是否满足了停止条件并退出迭代写入过程。 一旦迭代写入过程已被退出，存储器位置可以被识别为用特殊符号写入的候选。

公开(公告)号：US07119018B2

公开(公告)日：2006-10-10

申请号：US10887087

申请日：2004-07-09

申请人： Michael W. Lane ,  Stefanie R. Chiras ,  Terry A. Spooner ,  Robert Rosenberg ,  Daniel C. Edelstein

发明人： Michael W. Lane ,  Stefanie R. Chiras ,  Terry A. Spooner ,  Robert Rosenberg ,  Daniel C. Edelstein

IPC分类号： H01L21/44

CPC分类号： C25D5/10 ,  C25D5/50 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

摘要： A conducting material comprising: a conducting core region comprising copper and from 0.001 atomic percent to 0.6 atomic percent of one or more metals selected from iridium, osmium and rhenium; and an interfacial region. The interfacial region comprises at least 80 atomic percent or greater of the one or more metals. The invention is also directed to a method of making a conducting material comprising: providing an underlayer; contacting the underlayer with a seed layer, the seed layer comprising copper and one or more metals selected from iridium, osmium and rhenium; depositing a conducting layer comprising copper on the seed layer, and annealing the conducting layer at a temperature sufficient to cause grain growth in the conducting layer, yet minimize the migration of the one or more alloy metals from the seed layer to the conducting layer. The method further comprises polishing the conducting layer to provide a polished copper surface material, and annealing the polished copper surface material at a temperature to cause migration of the one or more metals from the seed layer to the polished surface to provide an interfacial region in contact with a copper conductor core region. The interfacial region and the copper conductor core region comprise the one or more metals.

公开(公告)号：US07102232B2

公开(公告)日：2006-09-05

申请号：US10827693

申请日：2004-04-19

申请人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Derren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Derren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

IPC分类号： H01L23/52

CPC分类号： H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

摘要翻译： 一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合 通过在两个电介质层之间引入粘附过渡层来改善N和H。 在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。 本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。 还提供了形成这种结构，特别是粘附过渡层的方法。

公开(公告)号：US20080254643A1

公开(公告)日：2008-10-16

申请号：US12143917

申请日：2008-06-23

申请人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Darren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Darren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

IPC分类号： H01L21/768

CPC分类号： H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

摘要翻译： 一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合 通过在两个电介质层之间引入粘附过渡层来改善N和H。 在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。 本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。 还提供了形成这种结构，特别是粘附过渡层的方法。

公开(公告)号：US07402532B2

公开(公告)日：2008-07-22

申请号：US11499220

申请日：2006-08-04

申请人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Derren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Derren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

IPC分类号： H01L23/48

CPC分类号： H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

摘要翻译： 一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合 通过在两个电介质层之间引入粘附过渡层来改善N和H。 在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。 本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。 还提供了形成这种结构，特别是粘附过渡层的方法。