公开(公告)号：US20080254643A1

公开(公告)日：2008-10-16

申请号：US12143917

申请日：2008-06-23

申请人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Darren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Darren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

IPC分类号： H01L21/768

CPC分类号： H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

摘要翻译： 一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合 通过在两个电介质层之间引入粘附过渡层来改善N和H。 在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。 本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。 还提供了形成这种结构，特别是粘附过渡层的方法。

公开(公告)号：US07820559B2

公开(公告)日：2010-10-26

申请号：US12143917

申请日：2008-06-23

申请人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Darren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Darren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

IPC分类号： H01L21/31 ,  H01L21/4763

CPC分类号： H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

摘要翻译： 一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合 通过在两个电介质层之间引入粘附过渡层来改善N和H。 在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。 本文提供的粘附过渡层包括下部含SiO x或SiON的区域和上部C分级区域。 还提供了形成这种结构，特别是粘附过渡层的方法。

公开(公告)号：US07402532B2

公开(公告)日：2008-07-22

申请号：US11499220

申请日：2006-08-04

申请人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Derren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Derren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

IPC分类号： H01L23/48

CPC分类号： H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

摘要翻译： 一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合 通过在两个电介质层之间引入粘附过渡层来改善N和H。 在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。 本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。 还提供了形成这种结构，特别是粘附过渡层的方法。

公开(公告)号：US07102232B2

公开(公告)日：2006-09-05

申请号：US10827693

申请日：2004-04-19

申请人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Derren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Derren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

IPC分类号： H01L23/52

CPC分类号： H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

摘要翻译： 一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合 通过在两个电介质层之间引入粘附过渡层来改善N和H。 在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。 本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。 还提供了形成这种结构，特别是粘附过渡层的方法。

公开(公告)号：US07951708B2

公开(公告)日：2011-05-31

申请号：US12477389

申请日：2009-06-03

申请人： Patrick W. DeHaven ,  Daniel C. Edelstein ,  Philip L. Flaitz ,  Takeshi Nogami ,  Stephen M. Rossnagel ,  Chih-Chao Yang

发明人： Patrick W. DeHaven ,  Daniel C. Edelstein ,  Philip L. Flaitz ,  Takeshi Nogami ,  Stephen M. Rossnagel ,  Chih-Chao Yang

IPC分类号： H01L21/44

CPC分类号： H01L21/2855 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  Y10T428/24917

摘要： A method of forming a diffusion barrier for use in semiconductor device manufacturing includes depositing, by a physical vapor deposition (PVD) process, an iridium doped, tantalum based barrier layer over a patterned interlevel dielectric (ILD) layer, wherein the barrier layer is deposited with an iridium concentration of at least 60 atomic % such that the barrier layer has a resulting amorphous structure.

摘要翻译： 形成用于半导体器件制造的扩散阻挡层的方法包括通过物理气相沉积（PVD）工艺将沉积有铱掺杂的钽基阻挡层沉积在图案化层间电介质（ILD）层上，其中阻挡层被沉积 其铱浓度至少为60原子％，使得阻挡层具有所得的无定形结构。

公开(公告)号：US20100311236A1

公开(公告)日：2010-12-09

申请号：US12477389

申请日：2009-06-03

申请人： Patrick W. DeHaven ,  Daniel C. Edelstein ,  Philip L. Flaitz ,  Takeshi Nogami ,  Stephen M. Rossnagel ,  Chih-Chao Yang

发明人： Patrick W. DeHaven ,  Daniel C. Edelstein ,  Philip L. Flaitz ,  Takeshi Nogami ,  Stephen M. Rossnagel ,  Chih-Chao Yang

IPC分类号： H01L21/768 ,  B05D5/12 ,  B32B15/00 ,  B32B3/10

CPC分类号： H01L21/2855 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  Y10T428/24917

摘要： A method of forming a diffusion barrier for use in semiconductor device manufacturing includes depositing, by a physical vapor deposition (PVD) process, an iridium doped, tantalum based barrier layer over a patterned interlevel dielectric (ILD) layer, wherein the barrier layer is deposited with an iridium concentration of at least 60% by atomic weight such that the barrier layer has a resulting amorphous structure.

摘要翻译： 形成用于半导体器件制造的扩散阻挡层的方法包括通过物理气相沉积（PVD）工艺将沉积有铱掺杂的钽基阻挡层沉积在图案化层间电介质（ILD）层上，其中阻挡层被沉积 其铱浓度至少为原子量的60％，使得阻挡层具有所得的无定形结构。

公开(公告)号：US06333531B1

公开(公告)日：2001-12-25

申请号：US09239655

申请日：1999-01-29

申请人： Yun-Yu Wang ,  Johnathan E. Faltermeier ,  Philip L. Flaitz ,  Jeffery L. Hurd ,  Rajarao Jammy ,  Radhika Srinivasan ,  Francis G. Trudeau ,  Dinah S. Weiss

发明人： Yun-Yu Wang ,  Johnathan E. Faltermeier ,  Philip L. Flaitz ,  Jeffery L. Hurd ,  Rajarao Jammy ,  Radhika Srinivasan ,  Francis G. Trudeau ,  Dinah S. Weiss

IPC分类号： H01L27108

CPC分类号： H01L27/10867

摘要： A process for forming a small grain structure in a material within a semiconductor device near the interface of an adjacent dissimilar material, to result in a highly diffusive grain structure. The highly diffusive grain structure formed within one material enhances diffusion of a dopant impurity, and provides for improved dopant control in an adjacent dissimilar material.

摘要翻译： 在邻近异种材料的界面附近的半导体器件内的材料中形成小晶粒结构的工艺，导致高扩散晶粒结构。 在一种材料内部形成的高度扩散的晶粒结构增强了掺杂杂质的扩散，并提供了在相邻不同材料中的改进的掺杂剂控制。

公开(公告)号：US06740568B2

公开(公告)日：2004-05-25

申请号：US10206875

申请日：2002-07-29

申请人： Yun Yu Wang ,  Johnathan Faltermeier ,  Colleen M. Snavely ,  Michael Maldei ,  Michael M. Iwatake ,  David M. Dobuzinsky ,  Ravikumar Ramachandran ,  Viraj Y. Sardesai ,  Philip L. Flaitz ,  Lisa Y. Ninomiya

发明人： Yun Yu Wang ,  Johnathan Faltermeier ,  Colleen M. Snavely ,  Michael Maldei ,  Michael M. Iwatake ,  David M. Dobuzinsky ,  Ravikumar Ramachandran ,  Viraj Y. Sardesai ,  Philip L. Flaitz ,  Lisa Y. Ninomiya

IPC分类号： H01L2136

CPC分类号： H01L21/02667 ,  H01L21/02046 ,  H01L21/02532 ,  H01L21/2022 ,  H01L21/28525 ,  H01L27/10873

摘要： In a method of forming a contact, a liner reactive ion etch is affected on a substrate to remove silicon nitride and silicon oxide. An oxygen plasma ex-situ clean, a Huang AB clean, and a dilute hydrofluric acid (DHF) clean are affected. Amorphous silicon is deposited and an anneal is performed to regrow and recrystallize amorphous silicon.

摘要翻译： 在形成接触的方法中，在衬底上影响衬里反应离子蚀刻以去除氮化硅和氧化硅。 氧等离子体原位清洗，黄AB清洁剂和稀释的氢氟酸（DHF）清洁剂都受到影响。 沉积非晶硅并进行退火以再结晶并重结晶非晶硅。

公开(公告)号：US06707086B1

公开(公告)日：2004-03-16

申请号：US09594638

申请日：2000-06-15

申请人： Rajarao Jammy ,  Philip L. Flaitz ,  Philip E. Batson ,  Hua Shen ,  Yun Yu Wang

发明人： Rajarao Jammy ,  Philip L. Flaitz ,  Philip E. Batson ,  Hua Shen ,  Yun Yu Wang

IPC分类号： H01L31119

CPC分类号： H01L21/28202 ,  C23C16/0218 ,  C23C16/345 ,  C23C16/56 ,  H01L21/3144 ,  H01L21/3185 ,  H01L27/10861 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66181 ,  H01L29/945

摘要： In accordance with the present invention, a method for forming a crystalline silicon nitride layer, includes the steps of providing a crystalline silicon substrate with an exposed surface, precleaning the exposed surface by employing a hydrogen prebake and exposing the exposed surface to nitrogen to form a crystalline silicon nitride layer. Also, a trench capacitor, in accordance with the present invention, includes a crystalline silicon substrate including deep trenches having surface substantially free of native oxide. A dielectric stack, including a crystalline silicon nitride layer, is formed on the sidewalls of the trenches. The dielectric stack forms a node dielectric between electrodes of the trench capacitor.

摘要翻译： 根据本发明，用于形成结晶氮化硅层的方法包括以下步骤：提供具有暴露表面的晶体硅衬底，通过使用氢预烘烤并将暴露表面暴露于氮以形成暴露表面， 晶体氮化硅层。 此外，根据本发明的沟槽电容器包括晶体硅衬底，其包括具有基本上不含天然氧化物的表面的深沟槽。 在沟槽的侧壁上形成包括结晶氮化硅层的电介质叠层。 电介质叠层在沟槽电容器的电极之间形成节点电介质。

公开(公告)号：US06746933B1

公开(公告)日：2004-06-08

申请号：US09999803

申请日：2001-10-26

申请人： Jochen Beintner ,  Rama Divakaruni ,  Johnathan Faltermeier ,  Philip L. Flaitz ,  Oleg Gluschenkov ,  Carol J. Heenan ,  Rajarao Jammy ,  Byeong Kim ,  Mihel Seitz ,  Akira Sudo ,  Yoichi Takegawa

发明人： Jochen Beintner ,  Rama Divakaruni ,  Johnathan Faltermeier ,  Philip L. Flaitz ,  Oleg Gluschenkov ,  Carol J. Heenan ,  Rajarao Jammy ,  Byeong Kim ,  Mihel Seitz ,  Akira Sudo ,  Yoichi Takegawa

IPC分类号： H01L21762

CPC分类号： H01L21/76224

摘要： An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.