公开(公告)号：US09478259B1

公开(公告)日：2016-10-25

申请号：US14704706

申请日：2015-05-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Chih-Wei Hu ,  Lee-Yin Lin

IPC: G11C5/02 ,  H01L27/115 ,  G11C16/24 ,  G11C16/14 ,  G11C16/26 ,  G11C5/06 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10

CPC classification number: H01L27/11582 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: The area consumed by switching transistors for a 3D NAND memory array can be reduced with 3D voltage switching transistors with reduced aggregate area in comparison with 2D voltage switching transistors such as transistors in the substrate. The integrated circuit comprises a 3D NAND array of memory transistors; a plurality of bit lines, with different ones of the plurality of bit lines electrically coupled to different parts of the 3D NAND array; and a plurality of transistor pairs with a stack of semiconductor layers. Different layers in the stack of semiconductor layers include different transistor pairs of the plurality of transistor pairs. Each of the plurality of transistor pairs includes first and second transistors with first, second, and third source/drain terminals. The first transistor includes the first and the third source/drain terminals, and the second transistor includes the second and the third source/drain terminals. The first source/drain terminal is electrically coupled to an erase voltage line. The second source/drain terminal is electrically coupled to a corresponding one of a plurality of program/read voltage lines. The third source/drain terminal is electrically coupled to a corresponding one of the plurality of bit lines.

Abstract translation: 与2D基板中的晶体管等2D电压开关晶体管相比，3D NAND存储器阵列的开关晶体管消耗的面积可以减小，具有减小的聚集面积的3D电压开关晶体管。 集成电路包括存储晶体管的3D NAND阵列; 多个位线，其中多个位线中的不同的位线电耦合到3D NAND阵列的不同部分; 以及具有堆叠半导体层的多个晶体管对。 半导体层堆叠中的不同层包括多个晶体管对的不同晶体管对。 多个晶体管对中的每一个包括具有第一，第二和第三源极/漏极端子的第一和第二晶体管。 第一晶体管包括第一和第三源极/漏极端子，第二晶体管包括第二和第三源极/漏极端子。 第一源极/漏极端子电耦合到擦除电压线。 第二源极/漏极端子电耦合到多个编程/读取电压线中的对应的一个。 第三源极/漏极端子电耦合到多个位线中的对应的一个位线。

公开(公告)号：US20190295652A1

公开(公告)日：2019-09-26

申请号：US15926217

申请日：2018-03-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Lee-Yin Lin

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34

Abstract: A memory device comprises a plurality of stacks of word lines, the word lines in the stacks having first vertical sides and second vertical sides opposite the first vertical sides, and a first plurality of strings and a second plurality of strings disposed respectively on the first vertical sides and the second vertical sides of the word lines in a particular stack in the plurality of stacks. The second plurality of strings is offset from the first plurality of strings in a direction along which the word lines in the particular stack extend. A first program operation includes applying a shielding voltage to a first string in the first plurality of strings and a fourth string in the second plurality of strings, and applying a program voltage to a second string in the second plurality of strings and a third string in the first plurality of strings.

公开(公告)号：US10418108B1

公开(公告)日：2019-09-17

申请号：US15926217

申请日：2018-03-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Lee-Yin Lin

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

Abstract: A memory device comprises a plurality of stacks of word lines, the word lines in the stacks having first vertical sides and second vertical sides opposite the first vertical sides, and a first plurality of strings and a second plurality of strings disposed respectively on the first vertical sides and the second vertical sides of the word lines in a particular stack in the plurality of stacks. The second plurality of strings is offset from the first plurality of strings in a direction along which the word lines in the particular stack extend. A first program operation includes applying a shielding voltage to a first string in the first plurality of strings and a fourth string in the second plurality of strings, and applying a program voltage to a second string in the second plurality of strings and a third string in the first plurality of strings.

公开(公告)号：US09330764B2

公开(公告)日：2016-05-03

申请号：US14305782

申请日：2014-06-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Lee-Yin Lin ,  Teng-Hao Yeh ,  Chih-Wei Hu ,  Chieh-Fang Chen

IPC: G11C11/34 ,  G11C16/08 ,  H01L21/768 ,  H01L21/266

CPC classification number: G11C16/08 ,  G11C8/14 ,  H01L21/266 ,  H01L21/28052 ,  H01L21/76895 ,  H01L27/11573 ,  H01L27/11578

Abstract: A device, such as an integrated circuit including memory, includes an array of memory cells on a substrate. A row/column line, such as a local word line or local bit line, is disposed in the array. The row/column line includes a pass transistor structure comprising a semiconductor strip in a first patterned layer over the substrate. The semiconductor strip includes a semiconductor channel body, a contact region on one side of the semiconductor channel body, and an extension on another side of the semiconductor channel body, which reaches into the memory cells in the array. A select line in a second patterned layer crossing the semiconductor channel body is provided. The pass transistor structure can be implemented in a fanout structure for row/column lines in the array.

Abstract translation: 诸如包括存储器的集成电路的装置包括衬底上的存储器单元的阵列。 行/列行，例如本地字线或局部位线，被布置在阵列中。 行/列线包括传输晶体管结构，其包括在衬底上的第一图案化层中的半导体条。 半导体条包括半导体通道主体，半导体通道主体一侧的接触区域和半导体通道体的另一侧的延伸部分，其延伸到阵列中的存储单元中。 提供了与半导体通道体交叉的第二图案化层中的选择线。 传输晶体管结构可以在阵列中的行/列线的扇出结构中实现。

公开(公告)号：US10790028B1

公开(公告)日：2020-09-29

申请号：US16576652

申请日：2019-09-19

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Lee-Yin Lin

IPC: G11C16/24 ,  G11C5/02 ,  H01L27/11582 ,  H01L27/11556 ,  G11C5/06

Abstract: An AND type flash memory includes a memory cell array, a plurality of page buffers and a plurality of voltage shifting circuits. The memory cell array is coupled to a plurality of bits lines and source lines. The page buffers are respectively coupled to the bit lines through a plurality of switches, and respectively provides a plurality of control signals. The control signals are transited between a first voltage and a reference voltage. The voltage shifting circuits respectively receive the control signals, generates a plurality of driving signals by shifting voltage values of the control signals, and provides the driving signals to the bit lines. Wherein, the driving signals are transited between a second voltage and the reference voltage, the second voltage is larger than the first voltage.

公开(公告)号：US20160329344A1

公开(公告)日：2016-11-10

申请号：US14704706

申请日：2015-05-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Chih-Wei Hu ,  Lee-Yin Lin

IPC: H01L27/115 ,  G11C16/14 ,  G11C16/26 ,  G11C16/24

CPC classification number: H01L27/11582 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: The area consumed by switching transistors for a 3D NAND memory array can be reduced with 3D voltage switching transistors with reduced aggregate area in comparison with 2D voltage switching transistors such as transistors in the substrate. The integrated circuit comprises a 3D NAND array of memory transistors; a plurality of bit lines, with different ones of the plurality of bit lines electrically coupled to different parts of the 3D NAND array; and a plurality of transistor pairs with a stack of semiconductor layers. Different layers in the stack of semiconductor layers include different transistor pairs of the plurality of transistor pairs. Each of the plurality of transistor pairs includes first and second transistors with first, second, and third source/drain terminals. The first transistor includes the first and the third source/drain terminals, and the second transistor includes the second and the third source/drain terminals. The first source/drain terminal is electrically coupled to an erase voltage line. The second source/drain terminal is electrically coupled to a corresponding one of a plurality of program/read voltage lines. The third source/drain terminal is electrically coupled to a corresponding one of the plurality of bit lines.

Abstract translation: 与2D基板中的晶体管等2D电压开关晶体管相比，3D NAND存储器阵列的开关晶体管消耗的面积可以减小，具有减小的聚集面积的3D电压开关晶体管。 集成电路包括存储晶体管的3D NAND阵列; 多个位线，其中多个位线中的不同的位线电耦合到3D NAND阵列的不同部分; 以及具有堆叠半导体层的多个晶体管对。 半导体层堆叠中的不同层包括多个晶体管对的不同晶体管对。 多个晶体管对中的每一个包括具有第一，第二和第三源极/漏极端子的第一和第二晶体管。 第一晶体管包括第一和第三源极/漏极端子，第二晶体管包括第二和第三源极/漏极端子。 第一源极/漏极端子电耦合到擦除电压线。 第二源极/漏极端子电耦合到多个编程/读取电压线中的对应的一个。 第三源极/漏极端子电耦合到多个位线中的对应的一个位线。