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公开(公告)号:US20150123171A1
公开(公告)日:2015-05-07
申请号:US14597128
申请日:2015-01-14
申请人: MARKO RADOSAVLJEVIC , PRASHANT MAJHI , JACK T. KAVALIEROS , NITI GOEL , WILMAN TSAI , NILOY MUKHERJEE , YONG JU LEE , GILBERT DEWEY , WILLY RACHMADY
发明人: MARKO RADOSAVLJEVIC , PRASHANT MAJHI , JACK T. KAVALIEROS , NITI GOEL , WILMAN TSAI , NILOY MUKHERJEE , YONG JU LEE , GILBERT DEWEY , WILLY RACHMADY
IPC分类号: H01L29/778 , H01L29/20
CPC分类号: H01L29/7786 , H01L21/2256 , H01L29/20 , H01L29/42316 , H01L29/47 , H01L29/66431 , H01L29/66462 , H01L29/7787
摘要: Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.
摘要翻译: 描述了III-V半导体器件的电导率改进。 第一改进包括与通道层不共同平面的阻挡层。 第二个改进包括金属/ Si,Ge或硅锗/ III-V堆叠的退火,以在Si和/或锗掺杂的III-V层上形成金属硅,金属锗或金属硅锗层。 然后,去除金属层并在金属硅,金属锗或金属硅锗层上形成源/漏电极。 第三个改进包括在III-V沟道层上形成IV族和/或VI族元素的层,以及退火以使IV族和/或VI族物质掺杂III-V通道层。 第四个改进包括在III-V器件的接近区域上形成的钝化层和/或偶极层。
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公开(公告)号:US20140175509A1
公开(公告)日:2014-06-26
申请号:US13723563
申请日:2012-12-21
申请人: BENJAMIN CHU-KUNG , VAN LE , ROBERT CHAU , SANSAPTAK DASGUPTA , GILBERT DEWEY , NITI GOEL , JACK KAVALIEROS , MATTHEW METZ , NILOY MUKHERJEE , RAVI PILLARISETTY , WILLY RACHMADY , MARKO RADOSAVLJEVIC , HAN WUI THEN , NANCY ZELICK
发明人: BENJAMIN CHU-KUNG , VAN LE , ROBERT CHAU , SANSAPTAK DASGUPTA , GILBERT DEWEY , NITI GOEL , JACK KAVALIEROS , MATTHEW METZ , NILOY MUKHERJEE , RAVI PILLARISETTY , WILLY RACHMADY , MARKO RADOSAVLJEVIC , HAN WUI THEN , NANCY ZELICK
IPC分类号: H01L29/06
CPC分类号: H01L29/7391 , H01L29/0676 , H01L29/66242 , H01L29/6625 , H01L29/66356 , H01L29/66393 , H01L29/732 , H01L29/735 , H01L29/737 , H01L29/7371 , H01L29/7436 , H01L29/785
摘要: An embodiment concerns forming an EPI film on a substrate where the EPI film has a different lattice constant from the substrate. The EPI film and substrate may include different materials to collectively form a hetero-epitaxial device having, for example, a Si and/or SiGe substrate and a III-V or IV film. The EPI film may be one of multiple EPI layers or films and the films may include different materials from one another and may directly contact one another. Further, the multiple EPI layers may be doped differently from another in terms of doping concentration and/or doping polarity. One embodiment includes creating a horizontally oriented hetero-epitaxial structure. Another embodiment includes a vertically oriented hetero-epitaxial structure. The hetero-epitaxial structures may include, for example, a bipolar junction transistor, heterojunction bipolar transistor, thyristor, and tunneling field effect transistor among others. Other embodiments are described herein.
摘要翻译: 一个实施例涉及在衬底上形成EPI膜,其中EPI膜具有与衬底不同的晶格常数。 EPI膜和衬底可以包括不同的材料以共同形成具有例如Si和/或SiGe衬底和III-V或IV膜的异质外延装置。 EPI膜可以是多个EPI层或膜中的一个,并且膜可以包括彼此不同的材料并且可以直接彼此接触。 此外,在掺杂浓度和/或掺杂极性方面,多个EPI层可以与另一个不同地被掺杂。 一个实施例包括产生水平取向的异质外延结构。 另一实施例包括垂直取向的异质外延结构。 异质外延结构可以包括例如双极结型晶体管,异质结双极晶体管,晶闸管和隧道场效应晶体管等。 本文描述了其它实施例。
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公开(公告)号:US20140175512A1
公开(公告)日:2014-06-26
申请号:US13722824
申请日:2012-12-20
申请人: BENJAMIN CHU-KUNG , VAN LE , ROBERT CHAU , SANSAPTAK DASGUPTA , GILBERT DEWEY , NITI GOEL , JACK KAVALIEROS , MATTHEW METZ , NILOY MUKHERJEE , RAVI PILLARISETTY , WILLY RACHMADY , MARKO RADOSAVLJEVIC , HAN WUI THEN , NANCY ZELICK
发明人: BENJAMIN CHU-KUNG , VAN LE , ROBERT CHAU , SANSAPTAK DASGUPTA , GILBERT DEWEY , NITI GOEL , JACK KAVALIEROS , MATTHEW METZ , NILOY MUKHERJEE , RAVI PILLARISETTY , WILLY RACHMADY , MARKO RADOSAVLJEVIC , HAN WUI THEN , NANCY ZELICK
IPC分类号: H01L29/78
CPC分类号: H01L21/823821 , H01L27/0924 , H01L29/1054 , H01L29/165 , H01L29/785
摘要: An embodiment uses a very thin layer nanostructure (e.g., a Si or SiGe fin) as a template to grow a crystalline, non-lattice matched, epitaxial (EPI) layer. In one embodiment the volume ratio between the nanostructure and EPI layer is such that the EPI layer is thicker than the nanostructure. In some embodiments a very thin bridge layer is included between the nanostructure and EPI. An embodiment includes a CMOS device where EPI layers covering fins (or that once covered fins) are oppositely polarized from one another. An embodiment includes a CMOS device where an EPI layer covering a fin (or that once covered a fin) is oppositely polarized from a bridge layer covering a fin (or that once covered a fin). Thus, various embodiments are disclosed from transferring defects from an EPI layer to a nanostructure (that is left present or removed). Other embodiments are described herein.
摘要翻译: 一个实施例使用非常薄的层纳米结构(例如,Si或SiGe鳍)作为模板来生长晶体,非晶格匹配的外延(EPI)层。 在一个实施方案中,纳米结构和EPI层之间的体积比使得EPI层比纳米结构厚。 在一些实施例中,在纳米结构和EPI之间包括非常薄的桥接层。 一个实施例包括一个CMOS器件,其中覆盖翅片(或一旦被覆盖的翅片)的EPI层彼此相反地极化。 一个实施例包括一个CMOS器件,其中覆盖翅片(或一旦被覆盖的翅片)的EPI层与覆盖翅片(或一旦被覆盖的翅片)的桥接层相反地偏振。 因此,从EPI层转移到纳米结构(剩下的存在或去除)的缺陷中公开了各种实施例。 本文描述了其它实施例。
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公开(公告)号:US20140175379A1
公开(公告)日:2014-06-26
申请号:US13721759
申请日:2012-12-20
申请人: BENJAMIN CHU-KUNG , VAN LE , ROBERT CHAU , SANSAPTAK DASGUPTA , GILBERT DEWEY , NITIKA GOEL , JACK KAVALIEROS , MATTHEW METZ , NILOY MUKHERJEE , RAVI PILLARISETTY , WILLY RACHMADY , MARKO RADOSAVLJEVIC , HAN WUI THEN , NANCY ZELICK
发明人: BENJAMIN CHU-KUNG , VAN LE , ROBERT CHAU , SANSAPTAK DASGUPTA , GILBERT DEWEY , NITIKA GOEL , JACK KAVALIEROS , MATTHEW METZ , NILOY MUKHERJEE , RAVI PILLARISETTY , WILLY RACHMADY , MARKO RADOSAVLJEVIC , HAN WUI THEN , NANCY ZELICK
IPC分类号: H01L29/06
CPC分类号: H01L29/1033 , H01L21/3086 , H01L29/04 , H01L29/0665 , H01L29/0669 , H01L29/0673 , H01L29/165 , H01L29/267 , H01L29/42392 , H01L29/66545 , H01L29/775 , H01L29/785 , H01L29/78696
摘要: An embodiment of the invention includes an epitaxial layer that directly contacts, for example, a nanowire, fin, or pillar in a manner that allows the layer to relax with two or three degrees of freedom. The epitaxial layer may be included in a channel region of a transistor. The nanowire, fin, or pillar may be removed to provide greater access to the epitaxial layer. Doing so may allow for a “all-around gate” structure where the gate surrounds the top, bottom, and sidewalls of the epitaxial layer. Other embodiments are described herein.
摘要翻译: 本发明的实施例包括外延层,其以允许该层以两个或三个自由度放松的方式直接接触例如纳米线,翅片或支柱。 外延层可以包括在晶体管的沟道区中。 可以去除纳米线,鳍或柱以提供对外延层的更大的访问。 这样做可以允许围绕外延层的顶部,底部和侧壁的“全向栅极”结构。 本文描述了其它实施例。
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公开(公告)号:US20110147712A1
公开(公告)日:2011-06-23
申请号:US12646589
申请日:2009-12-23
IPC分类号: H01L29/772 , H01L29/12 , H01L21/335
CPC分类号: H01L29/66636 , H01L29/66462 , H01L29/7783 , H01L29/7784
摘要: A quantum well device and a method for manufacturing the same are disclosed. In an embodiment, a quantum well structure comprises a quantum well region overlying a substrate and a remote counter doping comprising dopants of conductivity opposite to the conductivity of the charge carriers of the quantum well region. The remote counter doping is incorporated in a vicinity of the quantum well region for exchange mobile carriers with the quantum well channel, reducing the off-state leakage current. In another embodiment, a quantum well device comprises a quantum well structure including a remote counter doping, a gate region overlying a portion of the quantum well structure, and a source and drain region adjacent to the gate region. The quantum well device can also comprise a remote delta doping comprising dopants of the same conductivity as the quantum well channel.
摘要翻译: 公开了一种量子阱器件及其制造方法。 在一个实施例中,量子阱结构包括覆盖在衬底上的量子阱区域和包括与量子阱区域的电荷载流子的导电性相反的导电性的掺杂剂的远程计数器掺杂。 远程计数器掺杂被结合在量子阱区域附近,用于与量子阱沟道交换移动载流子,从而减小截止状态的漏电流。 在另一个实施例中,量子阱器件包括量子阱结构,其包括远程反相掺杂,覆盖量子阱结构的一部分的栅极区域和与栅极区域相邻的源极和漏极区域。 量子阱器件还可以包括包含与量子阱沟道相同导电性的掺杂剂的远程δ掺杂。
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公开(公告)号:US20150179798A1
公开(公告)日:2015-06-25
申请号:US14140042
申请日:2013-12-24
IPC分类号: H01L29/78 , H01L29/45 , H01L21/28 , H01L29/06 , H01L29/51 , H01L21/324 , H01L29/66 , H01L29/49
CPC分类号: H01L21/28088 , H01L21/28176 , H01L29/0676 , H01L29/42392 , H01L29/45 , H01L29/4966 , H01L29/4975 , H01L29/517 , H01L29/66795 , H01L29/7851 , H01L29/78696
摘要: The present disclosure relates to a method of forming a semiconductor. The method includes heating a substrate in a reaction chamber, supplying to the reaction chamber a first constituent including a metal borohydride wherein the metal borohydride includes at least one of: an alkaline earth metal, a transition metal, or a combination thereof; supplying to the reaction chamber a main-group hydride constituent; and depositing a metal compound on the substrate, wherein the metal compound comprises a) at least one of an alkaline earth metal a transition metal or a combination thereof, b) boron and c) optionally the main group alloying element.
摘要翻译: 本公开涉及形成半导体的方法。 该方法包括加热反应室中的基材,向反应室供应包括金属硼氢化物的第一组分,其中金属硼氢化物包括以下中的至少一种:碱土金属,过渡金属或其组合; 向反应室供应主要的氢化物组分; 以及在基底上沉积金属化合物,其中金属化合物包括a)碱土金属过渡金属或其组合中的至少一种,b)硼和c)任选的主族合金元素。
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