VERTICAL-CAVITY SURFACE-EMITTING LASER WITH CHARACTERISTIC WAVELENGTH OF 910 NM

    公开(公告)号:US20200381897A1

    公开(公告)日:2020-12-03

    申请号:US16890149

    申请日:2020-06-02

    IPC分类号: H01S5/183 H01S5/343

    摘要: A vertical-cavity surface-emitting laser (VCSEL) and method of fabrication thereof is provided. The VCSEL includes a mesa structure disposed on a substrate. The mesa structure has a first reflector stack, a second reflector stack, and an active region disposed between the first and second reflector stacks. The active region is configured to cause the VCSEL to emit light having a characteristic wavelength of 910 nanometers. The active region includes alternating layers of quantum wells and barriers, the quantum wells having high indium content (up to 18%). The VCSEL features a first contact layer disposed at least partially on a surface of the mesa structure and configured to serve as an electrical signal layer and a second contact layer disposed at least partially about the mesa structure and configured to serve as an electrical ground.

    Memory cell based on self-assembled monolayer polaron

    公开(公告)号:US11869566B2

    公开(公告)日:2024-01-09

    申请号:US17394515

    申请日:2021-08-05

    摘要: A memory device includes a memory cell and a controller. The memory cell includes: (a) an array of molecule chains, at least one molecule chain includes: (i) first and second binding sites positioned at first and second ends of the molecule chain, respectively, and (ii) a chain of one or more fullerene derivatives, chemically connecting between the first and second binding sites, (b) source and drain electrodes, electrically connected to the first and second binding sites, respectively, and configured to apply to the array a source-drain voltage (VSD) along a first axis, and (c) a gate electrode, configured to apply to the array a gate voltage (VG) along a second different axis. The controller is configured to perform a data storage operation in the memory cell by (i) applying to the gate electrode a signal for producing the VG, and (ii) applying the VSD between the source and drain electrodes.

    HIGH MODULATION SPEED PIN-TYPE PHOTODIODE

    公开(公告)号:US20220246781A1

    公开(公告)日:2022-08-04

    申请号:US17249140

    申请日:2021-02-22

    IPC分类号: H01L31/105 H01L31/0304

    摘要: Various embodiments of improved PIN-type photodiodes are provided. In an example embodiment, the PIN-type photodiode includes a p-type contact; an n-type contact; a first absorbing layer disposed between the p-type contact and the n-type contact; and a second absorbing layer disposed between the first absorbing layer and the n-type contact. The first absorbing layer is characterized by a first absorption coefficient and the second absorbing layer is characterized by a second absorption coefficient. The second absorption coefficient is greater than the first absorption coefficient. In another example embodiment, the PIN-type photodiode includes a p-type contact; an n-type contact; a first absorbing layer disposed between the p-type contact and the n-type contact; and a non-absorbing accelerating layer disposed between absorbing layers and non-absorbing drift layer and the n-type contact.

    VERTICAL-CAVITY SURFACE-EMITTING LASER LAYOUT FOR HIGH BANDWIDTH OUTPUT

    公开(公告)号:US20180375287A1

    公开(公告)日:2018-12-27

    申请号:US16015533

    申请日:2018-06-22

    摘要: A layout for a vertical-cavity surface-emitting laser (VCSEL) is provided. In an example embodiment, the layout comprises a VCSEL, an etched shape around a mesa of the VCSEL, a signal contact layer deposited on section of the mesa, and a ground contact layer. The ground contact layer comprises three parts and is positioned around a first section of the etched shape. The first part of the ground contact layer is deposited on a second section of the etched shape. The second and third parts of the ground contact layer comprise two legs off of the first part. The two legs are symmetrically positioned about two sides of the signal contact layer to form a ground-signal-ground configuration.

    System and method for characterizing the location of optical components in an optical module

    公开(公告)号:US10073227B1

    公开(公告)日:2018-09-11

    申请号:US15614036

    申请日:2017-06-05

    IPC分类号: G02B6/36 G02B6/42

    摘要: Systems and methods are described for characterizing the location of optical components relative to one another for optimizing the performance of the optical module. In particular, a mechanism is provided for a user to visually determine, from a fiber point of view, the alignment and relative positioning of a lens assembly of the optical module with an optoelectronic transceiver, such as a VCSEL or a photodiode. By characterizing a location of the lens assembly with respect to the optoelectronic transceiver in an x-y plane and/or determining a spacing of the components in a z-direction, the user can compensate for expected signal losses through the optical module due to inaccuracies in the relative positioning of the components, adjust the relative positioning of the components in the optical module being examined, or modify manufacturing parameters to improve the accuracy of positioning in the modules and PCBAs yet to be built.

    Memory cell based on self-assembled monolayer polaron

    公开(公告)号:US20230041969A1

    公开(公告)日:2023-02-09

    申请号:US17394515

    申请日:2021-08-05

    摘要: A memory device includes a memory cell and a controller. The memory cell includes: (a) an array of molecule chains, at least one molecule chain includes: (i) first and second binding sites positioned at first and second ends of the molecule chain, respectively, and (ii) a chain of one or more fullerene derivatives, chemically connecting between the first and second binding sites, (b) source and drain electrodes, electrically connected to the first and second binding sites, respectively, and configured to apply to the array a source-drain voltage (VSD) along a first axis, and (c) a gate electrode, configured to apply to the array a gate voltage (VG) along a second different axis. The controller is configured to perform a data storage operation in the memory cell by (i) applying to the gate electrode a signal for producing the VG, and (ii) applying the VSD between the source and drain electrodes.