公开(公告)号：US20180286693A1

公开(公告)日：2018-10-04

申请号：US15993568

申请日：2018-05-30

Applicant: Micron Technology, Inc.

Inventor： Baosuo Zhou ,  Mirzafer K. Abatchev ,  Ardavan Niroomand ,  Paul A. Morgan ,  Shuang Meng ,  Joseph Neil Greeley ,  Brian J. Coppa

IPC: H01L21/306 ,  H01L21/308 ,  H01L23/00 ,  H01L21/033

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

公开(公告)号：US09679781B2

公开(公告)日：2017-06-13

申请号：US14685525

申请日：2015-04-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mirzafer Abatchev ,  David Wells ,  Baosuo Zhou ,  Krupakar Murali Subramanian

IPC: H01R9/00 ,  H05K3/00 ,  H01L21/3105 ,  H01L21/033 ,  H01L21/306 ,  H01L21/311

CPC classification number: H01L21/31051 ,  H01L21/0337 ,  H01L21/306 ,  H01L21/30625 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31144 ,  Y10T29/49128 ,  Y10T29/49146 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49171 ,  Y10T29/49172 ,  Y10T29/49176 ,  Y10T29/4922 ,  Y10T29/49224

Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

公开(公告)号：US09003651B2

公开(公告)日：2015-04-14

申请号：US13936086

申请日：2013-07-05

Applicant: Micron Technology, Inc.

Inventor： Mirzafer Abatchev ,  David Wells ,  Baosuo Zhou ,  Krupakar Murali Subramanian

IPC: H01R9/00 ,  H05K3/00 ,  H01L21/306 ,  H01L21/033 ,  H01L21/3105

CPC classification number: H01L21/31051 ,  H01L21/0337 ,  H01L21/306 ,  H01L21/30625 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31144 ,  Y10T29/49128 ,  Y10T29/49146 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49171 ,  Y10T29/49172 ,  Y10T29/49176 ,  Y10T29/4922 ,  Y10T29/49224

Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

Abstract translation: 可以使用各种图案转移和蚀刻步骤来产生特征。 传统的光刻步骤可以与俯仰减小技术结合使用，以形成可以被整合成单一层的交叉细长特征的叠加的俯仰减小图案。 公开了使用填充层和保护层的平面化技术。 具有不同高度的集成电路的部分可以被蚀刻到公共平面。

公开(公告)号：US11335563B2

公开(公告)日：2022-05-17

申请号：US16807002

申请日：2020-03-02

Applicant: Micron Technology, Inc.

Inventor： Baosuo Zhou ,  Mirzafer K. Abatchev ,  Ardavan Niroomand ,  Paul A. Morgan ,  Shuang Meng ,  Joseph Neil Greeley ,  Brian J. Coppa

IPC: H01L21/306 ,  H01L21/033 ,  H01L21/308 ,  H01L23/00

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

公开(公告)号：US20160203993A1

公开(公告)日：2016-07-14

申请号：US15076474

申请日：2016-03-21

Applicant: Micron Technology, Inc.

Inventor： Baosuo Zhou ,  Mirzafer K. Abatchev ,  Ardavan Niroomand ,  Paul A. Morgan ,  Shuang Meng ,  Joseph Neil Greeley ,  Brian J. Coppa

IPC: H01L21/306

CPC classification number: H01L21/30625 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/3088 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

公开(公告)号：US20150021744A1

公开(公告)日：2015-01-22

申请号：US14507507

申请日：2014-10-06

Applicant: Micron Technology, Inc.

Inventor： Baosuo Zhou ,  Mirzafer K. Abatchev ,  Ardavan Niroomand ,  Paul A. Morgan ,  Shuang Meng ,  Joseph Neil Greely ,  Brian J. Coppa

IPC: H01L21/033 ,  H01L23/00

CPC classification number: H01L21/30625 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/3088 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

Abstract translation: 图案化层的方法使用一系列自对准间隔物增加在初始图案化层上形成的特征的密度。 提供待蚀刻的层，然后在待蚀刻的层上形成例如使用光学光刻形成的初始牺牲图案形成层。 根据实施例，图案化层可以被修整，然后形成并蚀刻一系列间隔层。 间隔层的数量及其目标尺寸取决于所需的特征密度增加。 还描述了一种过程中半导体器件和电子系统。

公开(公告)号：US20130105937A1

公开(公告)日：2013-05-02

申请号：US13725915

申请日：2012-12-21

Applicant: Micron Technology, Inc.

Inventor： Ardavan Niroomand ,  Baosuo Zhou ,  Ramakanth Alapati

IPC: H01L27/04

CPC classification number: H01L27/04 ,  H01L21/0338 ,  H01L21/3088 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.

Abstract translation: 一种用于制造半导体器件的方法包括对一层光致抗蚀剂材料进行构图以形成多个心轴。 该方法还包括通过原子层沉积（ALD）工艺在多个心轴上沉积氧化物材料。 该方法还包括从暴露的水平表面各向异性地蚀刻氧化物材料。 该方法还包括选择性地蚀刻光刻胶材料。

公开(公告)号：US10607844B2

公开(公告)日：2020-03-31

申请号：US15993568

申请日：2018-05-30

Applicant: Micron Technology, Inc.

Inventor： Baosuo Zhou ,  Mirzafer K. Abatchev ,  Ardavan Niroomand ,  Paul A. Morgan ,  Shuang Meng ,  Joseph Neil Greeley ,  Brian J. Coppa

IPC: H01L21/306 ,  H01L21/033 ,  H01L21/308 ,  H01L23/00

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

公开(公告)号：US10096483B2

公开(公告)日：2018-10-09

申请号：US15681066

申请日：2017-08-18

Applicant: Micron Technology, Inc.

Inventor： Baosuo Zhou ,  Mirzafer K. Abatchev ,  Ardavan Niroomand ,  Paul A. Morgan ,  Shuang Meng ,  Joseph Neil Greeley ,  Brian J. Coppa

IPC: H01L21/306 ,  H01L21/033 ,  H01L21/308 ,  H01L23/00

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

公开(公告)号：US09761457B2

公开(公告)日：2017-09-12

申请号：US15076474

申请日：2016-03-21

Applicant: Micron Technology, Inc.

Inventor： Baosuo Zhou ,  Mirzafer K. Abatchev ,  Ardavan Niroomand ,  Paul A. Morgan ,  Shuang Meng ,  Joseph Neil Greeley ,  Brian J. Coppa

IPC: H01L21/306 ,  H01L21/033 ,  H01L21/308 ,  H01L23/00

CPC classification number: H01L21/30625 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/3088 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.