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公开(公告)号：US12099734B2
公开(公告)日：2024-09-24
申请号：US17846761
申请日：2022-06-22
Applicant: Micron Technology, Inc.
Inventor： Deping He , Bo Zhou , Caixia Yang
CPC classification number: G06F3/064 , G06F3/061 , G06F3/0679 , G06F12/0246
Abstract: Methods, systems, and devices for memory block utilization in memory systems are described. A system configured to allow a memory device to group or segment a memory block into two or more sub-memory blocks, which can be independently programmed is described herein. For example, a host system may determine a configuration of a memory array, and communicate the configuration information to the memory system, and transmit a command for an operation to the memory system. In some examples, the memory system may utilize the memory array configuration information and determine to segment the blocks of memory cells into sub-blocks. By segmenting the memory block into sub-blocks, the memory device may maintain its memory block density while supporting efficient programming of blocks of the memory array.
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公开(公告)号：US12050794B2
公开(公告)日：2024-07-30
申请号：US17726255
申请日：2022-04-21
Applicant: Micron Technology, Inc.
CPC classification number: G06F3/064 , G06F1/28 , G06F3/0614 , G06F3/0673
Abstract: Methods, systems, and devices for read performance techniques for time retention are described. A memory system may store data in a block of memory cells and perform a power cycle operation. Based on performing the power cycle operation, the memory system may determine a first voltage offset associated with the block of memory cells by executing a first read command using an auto-read calibration operation. Based on the first voltage offset, and, in some examples, one or more additional voltage offsets, the memory system may calculate a retention time of data stored in the block of memory cells. The memory system may adjust a read voltage based on the retention time and perform one or more additional read commands.
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公开(公告)号：US20250013374A1
公开(公告)日：2025-01-09
申请号：US18766256
申请日：2024-07-08
Applicant: Micron Technology, Inc.
Abstract: Methods, systems, and devices for read performance techniques for time retention are described. A memory system may store data in a block of memory cells and perform a power cycle operation. Based on performing the power cycle operation, the memory system may determine a first voltage offset associated with the block of memory cells by executing a first read command using an auto-read calibration operation. Based on the first voltage offset, and, in some examples, one or more additional voltage offsets, the memory system may calculate a retention time of data stored in the block of memory cells. The memory system may adjust a read voltage based on the retention time and perform one or more additional read commands.
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公开(公告)号：US20230418491A1
公开(公告)日：2023-12-28
申请号：US17846761
申请日：2022-06-22
Applicant: Micron Technology, Inc.
Inventor： Deping He , Bo Zhou , Caixia Yang
IPC: G06F3/06
CPC classification number: G06F3/064 , G06F3/061 , G06F3/0679
Abstract: Methods, systems, and devices for memory block utilization in memory systems are described. A system configured to allow a memory device to group or segment a memory block into two or more sub-memory blocks, which can be independently programmed is described herein. For example, a host system may determine a configuration of a memory array, and communicate the configuration information to the memory system, and transmit a command for an operation to the memory system. In some examples, the memory system may utilize the memory array configuration information and determine to segment the blocks of memory cells into sub-blocks. By segmenting the memory block into sub-blocks, the memory device may maintain its memory block density while supporting efficient programming of blocks of the memory array.
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公开(公告)号：US11670375B2
公开(公告)日：2023-06-06
申请号：US17458211
申请日：2021-08-26
Applicant: Micron Technology, Inc.
Inventor： Hua Tan , Jingxun Eric Wu , Yingying Zhu , Hui Yang , Bo Zhou
CPC classification number: G11C16/10 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G11C16/0483 , G11C16/06 , G11C16/26 , G11C29/10 , G11C29/50
Abstract: A memory device provides a memory array including memory cells, a temperature sensing circuit, and a memory control unit operatively coupled to the memory array. The memory control unit includes a processor. The processor is configured to receive temperature information from the temperature sensing circuit, initiate programming of the memory cells with data using a first threshold voltage distribution when the temperature information indicates an operating temperature is in a first temperature range, and initiate programming of the memory cells with data using a second threshold voltage distribution when the temperature information indicates the operating temperature is in a second temperature range.
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Patent Agency Ranking
公开(公告)号：US11107533B2
公开(公告)日：2021-08-31
申请号：US16484881
申请日：2018-12-28
Applicant: Micron Technology, Inc.
Inventor： Hua Tan , Jingxun Eric Wu , Yingying Zhu , Hui Yang , Bo Zhou
Abstract: A memory array including memory cells, a temperature sensing circuit, and a memory control unit operatively coupled to the memory array. The memory control unit includes a processor. The processor is configured to receive temperature information from the temperature sensing circuit, initiate programming of the memory cells with data using a first threshold voltage distribution when the temperature information indicates an operating temperature is in a first temperature range, and initiate programming of the memory cells with data using a second threshold voltage distribution when the temperature information indicates the operating temperature is in a second temperature range.
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公开(公告)号：US20250123765A1
公开(公告)日：2025-04-17
申请号：US18830260
申请日：2024-09-10
Applicant: Micron Technology, Inc.
Inventor： Deping He , Bo Zhou , Caixia Yang
Abstract: Methods, systems, and devices for memory block utilization in memory systems are described. A system configured to allow a memory device to group or segment a memory block into two or more sub-memory blocks, which can be independently programmed is described herein. For example, a host system may determine a configuration of a memory array, and communicate the configuration information to the memory system, and transmit a command for an operation to the memory system. In some examples, the memory system may utilize the memory array configuration information and determine to segment the blocks of memory cells into sub-blocks. By segmenting the memory block into sub-blocks, the memory device may maintain its memory block density while supporting efficient programming of blocks of the memory array.
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公开(公告)号：US11900992B2
公开(公告)日：2024-02-13
申请号：US17649885
申请日：2022-02-03
Applicant: Micron Technology, Inc.
IPC: G11C16/04 , G11C11/4099 , G11C11/4074 , G11C11/4096 , G11C11/4076 , G11C11/408
CPC classification number: G11C11/4099 , G11C11/4074 , G11C11/4076 , G11C11/4085 , G11C11/4096
Abstract: Methods, systems, and devices for reference voltage adjustment for word line groups are described. In some examples, one or more components of a memory system may determine a duration that data has been stored to one or more memory cells. Based on the duration, a voltage value of one or more reference voltages may be adjusted accordingly. For example, a voltage value of one or more reference voltages may be adjusted based on the duration. Moreover, the reference voltage values may be adjusted differently in response to the memory cells having stored data for a relatively longer duration, as opposed to memory cells that have stored data for a relatively shorter duration. The adjusted reference voltages may be used during a subsequent read operation. The voltage value of the one or more reference voltages may be adjusted on a word-line group by word-line group basis.
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公开(公告)号：US20200219568A1
公开(公告)日：2020-07-09
申请号：US16484881
申请日：2018-12-28
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Hua Tan , Jingxun Eric Wu , Yingying Zhu , Hui Yang , Bo Zhou
Abstract: A memory device comprises a memory array including memory cells, a temperature sensing circuit, and a memory control unit operatively coupled to the memory array. The memory control unit includes a processor. The processor is configured to receive temperature information from the temperature sensing circuit, initiate programming of the memory cells with data using a first threshold voltage distribution when the temperature information indicates an operating temperature is in a first temperature range, and initiate programming of the memory cells with data using a second threshold voltage distribution when the temperature information indicates the operating temperature is in a second temperature range.
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公开(公告)号：US20240242760A1
公开(公告)日：2024-07-18
申请号：US18421729
申请日：2024-01-24
Applicant: Micron Technology, Inc.
IPC: G11C11/4099 , G11C11/4074 , G11C11/4076 , G11C11/408 , G11C11/4096
CPC classification number: G11C11/4099 , G11C11/4074 , G11C11/4076 , G11C11/4085 , G11C11/4096
Abstract: Methods, systems, and devices for reference voltage adjustment for word line groups are described. In some examples, one or more components of a memory system may determine a duration that data has been stored to one or more memory cells. Based on the duration, a voltage value of one or more reference voltages may be adjusted accordingly. For example, a voltage value of one or more reference voltages may be adjusted based on the duration. Moreover, the reference voltage values may be adjusted differently in response to the memory cells having stored data for a relatively longer duration, as opposed to memory cells that have stored data for a relatively shorter duration. The adjusted reference voltages may be used during a subsequent read operation. The voltage value of the one or more reference voltages may be adjusted on a word-line group by word-line group basis.
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