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公开(公告)号：US20220156185A1
公开(公告)日：2022-05-19
申请号：US16952813
申请日：2020-11-19
Applicant: Micron Technology, Inc.
Inventor： Nicola Colella , Antonino Pollio , Hua Tan
IPC: G06F12/0802 , G06F12/02
Abstract: Methods, systems, and devices for read operations for regions of a memory device are described. In some examples, a memory device may include a first cache for storing mappings between logical addresses and physical addresses of the memory device, and a second cache for storing indices associated with entries removed from the first cache. The memory device may include a controller configured to load mappings to the first cache upon receiving read commands. When the first cache is full, and when the memory device receives a read command, the controller may remove an entry from the first cache and may store an index associated with the removed entry to the second cache. The controller may then transmit a mapping associated with the index to a host device for use in a HPB operation.
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公开(公告)号：US12204442B2
公开(公告)日：2025-01-21
申请号：US17414299
申请日：2021-04-27
Applicant: Micron Technology, Inc.
Inventor： Hua Tan , Junjun Wang , De Hua Guo
Abstract: Methods, systems, and devices for dynamic voltage supply for memory circuit are described. An apparatus may adjust a supply voltage based on a process corner and a temperature of the memory system. An apparatus may include a memory array and a controller. The controller may determine a first temperature of the apparatus is less than a first temperature threshold at a first time. The controller may transition a voltage supplied to the controller from a first voltage level to a second voltage level based on determining the first temperature is less than the first temperature threshold. The controller may determine a second temperature is greater than a second temperature threshold at a second time. The controller may transition the voltage supplied to the controller from the second voltage level to the first voltage level based on determining the second temperature is greater than the second temperature threshold.
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公开(公告)号：US20240126685A1
公开(公告)日：2024-04-18
申请号：US17414299
申请日：2021-04-27
Applicant: Micron Technology, Inc.
Inventor： Hua Tan , Junjun Wang , De Hua Guo
IPC: G06F12/02
CPC classification number: G06F12/0246
Abstract: Methods, systems, and devices for dynamic voltage supply for memory circuit are described. An apparatus may adjust a supply voltage based on a process corner and a temperature of the memory system. An apparatus may include a memory array and a controller. The controller may determine a first temperature of the apparatus is less than a first temperature threshold at a first time. The controller may transition a voltage supplied to the controller from a first voltage level to a second voltage level based on determining the first temperature is less than the first temperature threshold. The controller may determine a second temperature is greater than a second temperature threshold at a second time. The controller may transition the voltage supplied to the controller from the second voltage level to the first voltage level based on determining the second temperature is greater than the second temperature threshold.
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公开(公告)号：US11886266B2
公开(公告)日：2024-01-30
申请号：US17736886
申请日：2022-05-04
Applicant: Micron Technology, Inc.
Inventor： Junjun Wang , Yanming Liu , Deping He , Hua Tan
IPC: G06F1/00 , G06F1/3225 , G06F1/3296 , G06F3/06 , G06F1/3203
CPC classification number: G06F1/3225 , G06F1/3296 , G06F3/0625 , G06F3/0659 , G06F1/3203 , G06F3/0679
Abstract: Methods, systems, and devices for dynamic power control are described. In some examples, a memory device may be configured to adjust a first duration for transitioning power modes. For example, the memory device may be configured to operate in a first power mode, a second power mode, and a third power mode. When operating in a second power mode, the memory device may be configured to increase or decrease the first duration for transitioning to a third power mode based on a second duration between received commands. If no commands are received during the first duration, the memory device may transition from the second power mode to the third power mode.
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公开(公告)号：US11670375B2
公开(公告)日：2023-06-06
申请号：US17458211
申请日：2021-08-26
Applicant: Micron Technology, Inc.
Inventor： Hua Tan , Jingxun Eric Wu , Yingying Zhu , Hui Yang , Bo Zhou
CPC classification number: G11C16/10 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G11C16/0483 , G11C16/06 , G11C16/26 , G11C29/10 , G11C29/50
Abstract: A memory device provides a memory array including memory cells, a temperature sensing circuit, and a memory control unit operatively coupled to the memory array. The memory control unit includes a processor. The processor is configured to receive temperature information from the temperature sensing circuit, initiate programming of the memory cells with data using a first threshold voltage distribution when the temperature information indicates an operating temperature is in a first temperature range, and initiate programming of the memory cells with data using a second threshold voltage distribution when the temperature information indicates the operating temperature is in a second temperature range.
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Patent Agency Ranking
公开(公告)号：US11107533B2
公开(公告)日：2021-08-31
申请号：US16484881
申请日：2018-12-28
Applicant: Micron Technology, Inc.
Inventor： Hua Tan , Jingxun Eric Wu , Yingying Zhu , Hui Yang , Bo Zhou
Abstract: A memory array including memory cells, a temperature sensing circuit, and a memory control unit operatively coupled to the memory array. The memory control unit includes a processor. The processor is configured to receive temperature information from the temperature sensing circuit, initiate programming of the memory cells with data using a first threshold voltage distribution when the temperature information indicates an operating temperature is in a first temperature range, and initiate programming of the memory cells with data using a second threshold voltage distribution when the temperature information indicates the operating temperature is in a second temperature range.
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公开(公告)号：US11687291B2
公开(公告)日：2023-06-27
申请号：US17580333
申请日：2022-01-20
Applicant: Micron Technology, Inc.
Inventor： Hua Tan , Fangwen Zhou , Wenjing Chen
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0656 , G06F3/0683 , G06F12/0238 , G06F2212/7201
Abstract: Methods, systems, and devices for memory operations are described. A first set of commands may be received for accessing a memory device. The first set of commands may include non-consecutive logical addresses that correspond to consecutively indexed physical addresses. A determination that the non-consecutive logical addresses correspond to consecutively indexed physical addresses may be determined based on a first mapping stored in a volatile memory. A second mapping may be transferred to the volatile memory based on the determination. The second mapping may include an indication of whether information stored at a set of physical address is valid. A second set of commands including non-consecutive logical addresses may be received for accessing the memory device. Data for the second set of commands that include the non-consecutive logical addresses may be retrieved from the memory device using the second mapping.
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公开(公告)号：US20220405205A1
公开(公告)日：2022-12-22
申请号：US17850584
申请日：2022-06-27
Applicant: Micron Technology, Inc
Inventor： Nicola Colella , Antonino Pollio , Hua Tan
IPC: G06F12/0802 , G06F12/02
Abstract: Methods, systems, and devices for read operations for regions of a memory device are described. In some examples, a memory device may include a first cache for storing mappings between logical addresses and physical addresses of the memory device, and a second cache for storing indices associated with entries removed from the first cache. The memory device may include a controller configured to load mappings to the first cache upon receiving read commands. When the first cache is full, and when the memory device receives a read command, the controller may remove an entry from the first cache and may store an index associated with the removed entry to the second cache. The controller may then transmit a mapping associated with the index to a host device for use in a HPB operation.
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公开(公告)号：US20200219568A1
公开(公告)日：2020-07-09
申请号：US16484881
申请日：2018-12-28
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Hua Tan , Jingxun Eric Wu , Yingying Zhu , Hui Yang , Bo Zhou
Abstract: A memory device comprises a memory array including memory cells, a temperature sensing circuit, and a memory control unit operatively coupled to the memory array. The memory control unit includes a processor. The processor is configured to receive temperature information from the temperature sensing circuit, initiate programming of the memory cells with data using a first threshold voltage distribution when the temperature information indicates an operating temperature is in a first temperature range, and initiate programming of the memory cells with data using a second threshold voltage distribution when the temperature information indicates the operating temperature is in a second temperature range.
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公开(公告)号：US11886341B2
公开(公告)日：2024-01-30
申请号：US17850584
申请日：2022-06-27
Applicant: Micron Technology, Inc.
Inventor： Nicola Colella , Antonino Pollio , Hua Tan
IPC: G06F12/00 , G06F12/0802 , G06F12/02
CPC classification number: G06F12/0802 , G06F12/0223 , G06F2212/604 , G06F2212/608
Abstract: Methods, systems, and devices for read operations for regions of a memory device are described. In some examples, a memory device may include a first cache for storing mappings between logical addresses and physical addresses of the memory device, and a second cache for storing indices associated with entries removed from the first cache. The memory device may include a controller configured to load mappings to the first cache upon receiving read commands. When the first cache is full, and when the memory device receives a read command, the controller may remove an entry from the first cache and may store an index associated with the removed entry to the second cache. The controller may then transmit a mapping associated with the index to a host device for use in a HPB operation.
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