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公开(公告)号：US20250159912A1
公开(公告)日：2025-05-15
申请号：US18909685
申请日：2024-10-08
Applicant: Micron Technology, Inc.
Inventor： Dojun Kim , Sanket S. Kelkar , An-Jen B. Cheng , Christopher W. Petz , Ryan J. Waskiewicz , Michael Mutch , Ashwin Panday , Sarah bull
Abstract: An apparatus comprising one or more capacitors that comprise a bottom electrode, a high-k dielectric material, and a top electrode. The bottom electrode comprises an oxygen-doped titanium nitride material and one or more undoped titanium nitride materials. The oxygen-doped titanium nitride material is on sidewalls of the one or more undoped titanium nitride materials and the one or more undoped titanium nitride materials extending between sidewalls of the oxygen-doped titanium nitride material. Electronic devices and methods of forming an electronic device are also disclosed.
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公开(公告)号：US20220028968A1
公开(公告)日：2022-01-27
申请号：US17498046
申请日：2021-10-11
Applicant: Micron Technology, Inc.
Inventor： Sanket S. Kelkar , Christopher W. Petz , Dojun Kim , Matthew N. Rocklein , Brenda D. Kraus
IPC: H01L49/02 , H01L21/285
Abstract: Methods, apparatuses, and systems related to forming a barrier material between an electrode and a dielectric material are described. An example method includes forming a dielectric material on a bottom electrode material of a storage node in a semiconductor fabrication process. The method further includes forming a barrier material on the dielectric material to reduce oxygen vacancies in the dielectric material. The method further includes forming a top electrode on the barrier material.
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公开(公告)号：US11145710B1
公开(公告)日：2021-10-12
申请号：US16913549
申请日：2020-06-26
Applicant: Micron Technology, Inc.
Inventor： Sanket S. Kelkar , Christopher W. Petz , Dojun Kim , Matthew N. Rocklein , Brenda D. Kraus
IPC: H01L21/8242 , H01L27/108 , H01L49/02 , H01L21/285
Abstract: Methods, apparatuses, and systems related to forming a barrier material between an electrode and a dielectric material are described. An example method includes forming a dielectric material on a bottom electrode material of a storage node in a semiconductor fabrication process. The method further includes forming a barrier material on the dielectric material to reduce oxygen vacancies in the dielectric material. The method further includes forming a top electrode on the barrier material.
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公开(公告)号：US11101274B2
公开(公告)日：2021-08-24
申请号：US16704657
申请日：2019-12-05
Applicant: Micron Technology, Inc.
Inventor： Clement Jacob , Vassil N. Antonov , Jaydeb Goswami , Albert Liao , Christopher W. Petz , Durai Vishak Nirmal Ramaswamy
IPC: H01L21/00 , H01L27/11507 , H01L21/02 , H01L49/02
Abstract: A ferroelectric capacitor comprises two conductive capacitor electrodes having ferroelectric material there-between. At least one of the capacitor electrodes comprise MxSiOy, where “M” is at least one of Ru, Ti, Ta, Co, Pt, Ir. Os, Mo, V, W, Sr, Re, Rh, Pd, La, Zn, In, Sn, and Nb. Other aspects, including method, are disclosed.
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公开(公告)号：US20200212046A1
公开(公告)日：2020-07-02
申请号：US16235957
申请日：2018-12-28
Applicant: Micron Technology, Inc.
Inventor： Kentaro Ishii , Yongjun J. Hu , Amirhasan Nourbakhsh , Durai Vishak Nirmal Ramaswamy , Christopher W. Petz , Luca Fumagalli
IPC: H01L27/108
Abstract: A method of forming an apparatus comprises forming a first metal nitride material over an upper surface of a conductive material within an opening extending through at least one dielectric material through a non-conformal deposition process. A second metal nitride material is formed over an upper surface of the first metal nitride material and side surfaces of the at least one dielectric material partially defining boundaries of the opening through a conformal deposition process. A conductive structure is formed over surfaces of the second metal nitride material within the opening. Apparatuses and electronic systems are also described.
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Patent Agency Ranking
公开(公告)号：US10700091B2
公开(公告)日：2020-06-30
申请号：US16431527
申请日：2019-06-04
Applicant: Micron Technology, Inc.
Inventor： David Ross Economy , John Mark Meldrim , Haoyu Li , Yongjun Jeff Hu , Christopher W. Petz , Daniel Billingsley , Everett A. McTeer
IPC: H01L27/11582 , H01L27/11556 , H01L27/11519 , H01L21/311 , H01L27/11565 , H01L21/768 , H01L27/1157
Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.
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公开(公告)号：US10546848B2
公开(公告)日：2020-01-28
申请号：US16398433
申请日：2019-04-30
Applicant: Micron Technology, Inc.
Inventor： Daniel Billingsley , Everett A. McTeer , Christopher W. Petz , Haoyu Li , John Mark Meldrim , Yongjun Jeff Hu
Abstract: An integrated assembly includes an insulative mass with a first region adjacent to a second region. The first region has a greater amount of one or more inert interstitial elements incorporated therein than does the second region. Some embodiments include an integrated assembly which has vertically-extending channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure includes doped semiconductor material in direct contact with bottom regions of the channel material pillars. An insulative mass is along the bottom regions of the channel material pillars. The insulative mass has an upper region over a lower region. The lower region has a greater amount of one or more inert interstitial elements incorporated therein than does the upper region. Some embodiments include methods of forming integrated assemblies.
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8.发明申请公开(公告)号：US20190267383A1
公开(公告)日：2019-08-29
申请号：US15903964
申请日：2018-02-23
Applicant: Micron Technology, Inc.
Inventor： Matthew N. Rocklein , Paul A. Paduano , Sanket S. Kelkar , Christopher W. Petz , Zhe Song , Vassil Antonov , Qian Tao
IPC: H01L27/108 , H01L49/02 , H01L21/285
Abstract: A DRAM capacitor comprising a first capacitor electrode configured as a container and comprising a doped titanium nitride material, a capacitor dielectric on the first capacitor electrode, and a second capacitor electrode on the capacitor dielectric. Methods of forming the DRAM capacitor are also disclosed, as are semiconductor devices and systems comprising such DRAM capacitors.
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公开(公告)号：US10355014B1
公开(公告)日：2019-07-16
申请号：US15852989
申请日：2017-12-22
Applicant: Micron Technology, Inc.
Inventor： David Ross Economy , John Mark Meldrim , Haoyu Li , Yongjun Jeff Hu , Christopher W. Petz , Daniel Billingsley , Everett A. McTeer
IPC: H01L27/11582 , H01L27/11556 , H01L27/11519 , H01L21/311 , H01L27/11565 , H01L21/768
Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.
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公开(公告)号：US20150123065A1
公开(公告)日：2015-05-07
申请号：US14070423
申请日：2013-11-01
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Christopher W. Petz , Dale W. Collins , Scott E. Sills , Shuichiro Yasuda
IPC: H01L45/00
CPC classification number: H01L45/1246 , H01L45/085 , H01L45/12 , H01L45/1233 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/1608
Abstract: Some embodiments include a memory cell that has an electrode, a switching material over the electrode, a buffer region over the switching material, and an ion reservoir material over the buffer region. The buffer region includes one or more elements from Group 14 of the periodic table in combination with one or more chalcogen elements. Some embodiments include methods of forming memory cells.
Abstract translation: 一些实施例包括具有电极，电极上方的开关材料，开关材料上方的缓冲区域以及缓冲区域上方的离子储存器材料的存储器单元。 缓冲区域包括与一个或多个硫属元素组合的周期表第14族中的一个或多个元素。 一些实施例包括形成存储器单元的方法。
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