公开(公告)号：US20250159865A1

公开(公告)日：2025-05-15

申请号：US18933964

申请日：2024-10-31

Applicant: Micron Technology, Inc.

Inventor： Yuanzhi Ma ,  Scott E. Sills ,  Si-Woo Lee

IPC: H10B12/00 ,  H10B53/20 ,  H10B53/30

Abstract: Methods, systems, and devices for self-aligned capacitors for three-dimensional memory systems are described. For example, a capacitor of a memory cell may include multiple interfaces (e.g., concentric interfaces, dielectric interfaces, interfaces at different relative radial positions from an axis of the capacitor) between material portions of a first electrode and a second electrode, each across a respective portion of a dielectric material. A separating dielectric feature may be included between the capacitor and a cell selection transistor of the memory cell, which may support self-alignment of features of the capacitor with features of the cell selection transistor (e.g., self-alignment for fabrication operations associated with forming the capacitor).

公开(公告)号：US20250098213A1

公开(公告)日：2025-03-20

申请号：US18970438

申请日：2024-12-05

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Ramanathan Gandhi ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L29/786 ,  H01L29/66 ,  H10B63/00

Abstract: A method of forming a device comprises forming dielectric structures over other dielectric structures overlying conductive contact structures, the dielectric structures separated from one another by trenches and laterally extending orthogonal to the other dielectric structures and the conductive contact structures. Conductive gate structures are formed on exposed side surfaces of the dielectric structures within the trenches. Dielectric oxide structures are formed on exposed side surfaces of the conductive gate structures within the trenches. Exposed portions of the other dielectric structures are removed to form isolation structures. Semiconductive pillars are formed on exposed side surfaces of the dielectric oxide structures and the isolation structures within the trenches. The semiconductive pillars are in electrical contact with the conductive contact structures. Additional conductive contact structures are formed on upper surfaces of the semiconductive pillars. A device, a memory device, and an electronic system are also described.

公开(公告)号：US20250081535A1

公开(公告)日：2025-03-06

申请号：US18784338

申请日：2024-07-25

Applicant: Micron Technology, Inc.

Inventor： Adharsh Rajagopal ,  Scott E. Sills ,  Yi Fang Lee ,  Glen H. Walters ,  Alexandre Marc Subirats ,  Yuanzhi Ma

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

Abstract: Systems, methods and apparatus are provided for transistors having a channel region comprising a crystalline spinel indium-gallium-zinc-oxide (IGZO) material.

公开(公告)号：US20240098970A1

公开(公告)日：2024-03-21

申请号：US17946925

申请日：2022-09-16

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Si-Woo Lee ,  David K. Hwang ,  Yoshitaka Nakamura ,  Yuanzhi Ma ,  Glen H. Walters

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/10882

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by silicon (Si) channel regions. A digit line having a global digit line (GDL) contact is formed in a trench adjacent to the first source/drain regions. In one example, the digit line is electrically isolated from a neighboring digit line at the bottom of the trench. In another example, the digit line is formed continuously along a bottom surface of trench to form shared digit lines between horizontal access devices, in two separate arrays, on opposing second vertical surfaces. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and vertical digit lines coupled to the first source/drain regions.

公开(公告)号：US20240074141A1

公开(公告)日：2024-02-29

申请号：US17895017

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： Yoshitaka Nakamura ,  Yuanzhi Ma ,  Scott E. Sills ,  Si-Woo Lee ,  David K. Hwang

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/10805 ,  H01L27/1085 ,  H01L27/10873 ,  H01L29/66742 ,  H01L29/78696

Abstract: Methods and devices for a lateral three-dimensional memory device, are described herein. One method includes forming a thin film transistor including a first thermal process having a first range of temperatures, forming a capacitor bottom electrode of a capacitor structure including a second thermal process having a second range of temperature, wherein a maximum temperature in the second range of temperatures is less than a maximum temperature in the first range of temperatures, forming a CMOS structure including a third thermal process having a third range of temperatures, wherein a maximum temperature in the third range of temperatures is less than a maximum temperature in the second range of temperatures, and forming at least one other part of the capacitor structure.

公开(公告)号：US11898733B2

公开(公告)日：2024-02-13

申请号：US18194907

申请日：2023-04-03

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills

IPC: F21V29/00 ,  F21V29/67 ,  F21V9/30 ,  F21V29/83 ,  F21V7/00 ,  F21V13/14 ,  F21V29/507 ,  F21V29/74 ,  F21V29/80 ,  F21Y115/10 ,  F21V7/05 ,  F21V13/04 ,  H01L33/48 ,  H01L33/60

CPC classification number: F21V29/67 ,  F21V7/0008 ,  F21V9/30 ,  F21V13/14 ,  F21V29/673 ,  F21V29/83 ,  F21V7/005 ,  F21V7/05 ,  F21V13/04 ,  F21V29/507 ,  F21V29/74 ,  F21V29/80 ,  F21Y2115/10 ,  H01L33/48 ,  H01L33/60

Abstract: A solid state lighting (SSL) with a solid state emitter (SSE) having thermally conductive projections extending into an air channel, and methods of making and using such SSLs. The thermally conductive projections can be fins, posts, or other structures configured to transfer heat into a fluid medium, such as air. The projections can be electrical contacts between the SSE and a power source. The air channel can be oriented generally vertically such that air in the channel warmed by the SSE flows upward through the channel.

公开(公告)号：US20230397391A1

公开(公告)日：2023-12-07

申请号：US17888467

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Scott E. Sills ,  David K. Hwang ,  Yoshitaka Nakamura ,  Yuanzhi Ma ,  Glen H. Walters

IPC: H01L27/108

CPC classification number: H01L27/10873 ,  H01L27/10805 ,  H01L27/1085 ,  H01L27/10885

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. A support structure is provided to the epitaxially grown, single crystalline Si. Horizontally oriented access lines connect to gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures separated from the channel regions by gate dielectrics. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and vertical digit lines coupled to the first source/drain regions.

公开(公告)号：US20230317798A1

公开(公告)日：2023-10-05

申请号：US17712294

申请日：2022-04-04

Applicant: Micron Technology, Inc.

Inventor： Adharsh Rajagopal ,  Scott E. Sills ,  Sumeet C. Pandey ,  David M. Guzman

IPC: H01L29/24 ,  H01L27/108 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/24 ,  H01L27/108 ,  H01L29/7869 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/02631 ,  H01L29/66969

Abstract: Systems, methods and apparatus are provided for transistors having a first source/drain region, a second source/drain region, and a channel region, wherein the channel region comprises an antimony-gallium-zinc-oxide (SbGZO) material.

公开(公告)号：US11742344B2

公开(公告)日：2023-08-29

申请号：US17647138

申请日：2022-01-05

Applicant: Micron Technology, Inc.

Inventor： Kurt D. Beigel ,  Scott E. Sills

IPC: H01L27/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L21/822 ,  H01L21/8238 ,  G11C29/44 ,  G11C5/02 ,  G11C29/14 ,  G11C29/12 ,  G11C7/10 ,  H01L29/66 ,  G11C29/00 ,  G11C29/42 ,  H10B99/00 ,  G11C7/12 ,  G11C5/14 ,  H03K19/20 ,  H03K19/0948 ,  G11C8/10 ,  G11C8/08

CPC classification number: H01L27/0688 ,  G11C5/025 ,  G11C7/10 ,  G11C29/1201 ,  G11C29/14 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/72 ,  G11C29/81 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/0642 ,  H01L29/42392 ,  H01L29/6675 ,  H01L29/78642 ,  H01L29/78696 ,  H10B99/00 ,  G11C5/145 ,  G11C5/147 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  H03K19/0948 ,  H03K19/20

Abstract: A semiconductor device includes a stack structure comprising decks. Each deck of the stack structure comprises a memory element level comprising memory elements and control logic level in electrical communication with the memory element level, the control logic level comprising a first subdeck structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region and a second subdeck structure comprising a second number of transistors comprising the other of the P-type channel region or the N-type channel region overlying the first subdeck structure. Related semiconductor devices and methods of forming the semiconductor devices are disclosed.

公开(公告)号：US11735479B2

公开(公告)日：2023-08-22

申请号：US17532856

申请日：2021-11-22

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Kurt D. Beigel

IPC: H01L27/12 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/528 ,  H01L27/092 ,  H01L23/522 ,  H01L27/06 ,  H10B69/00 ,  H01L29/786 ,  H01L29/78

CPC classification number: H01L21/8221 ,  H01L21/823871 ,  H01L21/823885 ,  H01L21/84 ,  H01L23/528 ,  H01L23/5226 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1207 ,  H10B69/00 ,  H01L29/7827 ,  H01L29/78642

Abstract: Some embodiments include an assembly having a CMOS tier. The CMOS tier includes a PMOS deck and an NMOS deck, with the decks being vertically offset relative to one another. The PMOS deck has p-channel transistors which are substantially identical to one another, and the NMOS deck has n-channel transistors which are substantially identical to one another. An insulative region is between the PMOS deck and the NMOS deck. The CMOS tier has one or more circuit components which include one or more of the n-channel transistors coupled with one or more of the p-channel transistors through one or more conductive interconnects extending through the insulative region. Some embodiments include methods of forming assemblies to comprise one or more CMOS tiers.