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    Access line dependent biasing schemes
    1.
    发明授权
    Access line dependent biasing schemes 有权
    接入线相关偏置方案

    公开(公告)号：US08730734B2

    公开(公告)日：2014-05-20

    申请号：US13746114

    申请日：2013-01-21

    Applicant: Micron Technology, Inc.

    Inventor： Dzung H. Nguyen

    IPC: G11C11/34

    CPC classification number: G11C16/04 ,  G11C8/08 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/08

    Abstract: The present disclosure includes methods, devices, and systems for access line biasing. One embodiment includes selecting, using a controller external to the memory device, a particular access line dependent biasing scheme and corresponding bias conditions for use in performing an access operation on an array of memory cells of the memory device, and performing the access operation using the selected particular access line dependent biasing scheme and corresponding bias conditions. In one or more embodiments, the selected particular access line dependent biasing scheme and corresponding bias conditions is selected by the controller external to the memory device based, at least partially, on a target access line of the array.

    Abstract translation: 本公开包括用于接入线偏置的方法，设备和系统。 一个实施例包括：使用存储器设备外部的控制器选择特定的访问线路依赖偏置方案和相应的偏置条件，以用于对存储器件的存储器单元阵列执行访问操作，以及使用 所选择的特定接入线相关偏置方案和相应的偏置条件。 在一个或多个实施例中，所选择的特定访问线路依赖偏置方案和对应的偏置条件由存储器设备外部的至少部分地基于阵列的目标访问线路选择。

    Replacing defective memory blocks in response to external addresses
    2.
    发明授权
    Replacing defective memory blocks in response to external addresses 有权
    更换有缺陷的内存块以响应外部地址

    公开(公告)号：US08705299B2

    公开(公告)日：2014-04-22

    申请号：US13894543

    申请日：2013-05-15

    Applicant: Micron Technology, Inc.

    Inventor： Vishal Sarin ,  Dzung H. Nguyen ,  William H. Radke

    IPC: G11C7/00

    CPC classification number: G11C29/04 ,  G11C29/808 ,  G11C29/82 ,  G11C29/848

    Abstract: An apparatus has a controller. The controller is configured to address a non-defective memory block of a sequence of memory blocks in place of a defective memory block of the sequence of memory blocks such that the non-defective memory block replaces the defective memory block. The non-defective memory block is a proximate non-defective memory block following the defective memory block in the sequence of memory blocks that is available to replace the defective memory block. The controller is configured to apply a voltage-delay correction to the non-defective memory block that replaces the defective memory block based on the actual location of the non-defective memory block.

    Abstract translation: 装置具有控制器。 控制器被配置为代替存储器块序列的缺陷存储器块来寻址一系列存储器块的无缺陷存储器块，使得非缺陷存储器块替换有缺陷的存储器块。 无缺陷存储器块是跟随可用于替换有缺陷的存储器块的存储器块序列中的缺陷存储器块之后的邻近的无缺陷存储器块。 所述控制器被配置为基于所述无缺陷存储器块的实际位置对所述缺陷存储器块进行替换的所述非缺陷存储器块施加电压延迟校正。

    REPLACING DEFECTIVE MEMORY BLOCKS IN RESPONSE TO EXTERNAL ADDRESSES
    5.
    发明申请
    REPLACING DEFECTIVE MEMORY BLOCKS IN RESPONSE TO EXTERNAL ADDRESSES 有权
    对外部地址更换有缺陷的记忆块

    公开(公告)号：US20130250707A1

    公开(公告)日：2013-09-26

    申请号：US13894543

    申请日：2013-05-15

    Applicant: Micron Technology, Inc.

    Inventor： Sarin Vishal ,  Dzung H. Nguyen ,  William H. Radke

    IPC: G11C29/04

    CPC classification number: G11C29/04 ,  G11C29/808 ,  G11C29/82 ,  G11C29/848

    Abstract: An apparatus has a controller. The controller is configured to address a non-defective memory block of a sequence of memory blocks in place of a defective memory block of the sequence of memory blocks such that the non-defective memory block replaces the defective memory block. The non-defective memory block is a proximate non-defective memory block following the defective memory block in the sequence of memory blocks that is available to replace the defective memory block. The controller is configured to apply a voltage-delay correction to the non-defective memory block that replaces the defective memory block based on the actual location of the non-defective memory block.

    Abstract translation: 装置具有控制器。 控制器被配置为代替存储器块序列的缺陷存储器块来寻址一系列存储器块的无缺陷存储器块，使得非缺陷存储器块替换有缺陷的存储器块。 无缺陷存储器块是跟随可用于替换有缺陷的存储器块的存储器块序列中的缺陷存储器块之后的邻近的无缺陷存储器块。 所述控制器被配置为基于所述无缺陷存储器块的实际位置对所述缺陷存储器块进行替换的所述非缺陷存储器块施加电压延迟校正。

    SENSING OPERATIONS IN A MEMORY DEVICE
    6.
    发明申请
    SENSING OPERATIONS IN A MEMORY DEVICE 有权
    感应器中的感应操作

    公开(公告)号：US20150355849A1

    公开(公告)日：2015-12-10

    申请号：US14827371

    申请日：2015-08-17

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Jonathan Pabustan ,  Vishal Sarin ,  Dzung H. Nguyen

    IPC: G06F3/06 ,  G11C16/34 ,  G11C16/32 ,  G11C16/08

    CPC classification number: G06F3/0613 ,  G06F3/0655 ,  G06F3/0679 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3454 ,  G11C16/3459

    Abstract: Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells being sensed. Target data for each memory cell is stored in a data cache associated with that particular memory cell. When it is detected that a memory cell has turned on, the translated count output associated with the count output that is indicative of the voltage level that turned on the memory cell is compared to the target data. The comparison determines the state of the memory cell.

    Abstract translation: 公开了感测方法，编程方法，存储器件和存储器系统。 在一种用于感测的方法中，计数电路产生计数输出和转换计数输出。 计数输出被转换成时变电压，该电压偏置耦合到被感测的存储器单元的字线。 每个存储器单元的目标数据被存储在与该特定存储器单元相关联的数据高速缓存器中。 当检测到存储器单元已经接通时，将与指示存储器单元接通的电压电平的计数输出相关联的转换计数输出与目标数据进行比较。 比较确定存储单元的状态。

    SENSING OPERATIONS IN A MEMORY DEVICE
    8.
    发明申请
    SENSING OPERATIONS IN A MEMORY DEVICE 有权
    感应器中的感应操作

    公开(公告)号：US20140104956A1

    公开(公告)日：2014-04-17

    申请号：US14104444

    申请日：2013-12-12

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Jonathan Pabustan ,  Vishal Sarin ,  Dzung H. Nguyen

    IPC: G11C16/10

    CPC classification number: G06F3/0613 ,  G06F3/0655 ,  G06F3/0679 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3454 ,  G11C16/3459

    Abstract: Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells being sensed. Target data for each memory cell is stored in a data cache associated with that particular memory cell. When it is detected that a memory cell has turned on, the translated count output associated with the count output that is indicative of the voltage level that turned on the memory cell is compared to the target data. The comparison determines the state of the memory cell.

    Abstract translation: 公开了感测方法，编程方法，存储器件和存储器系统。 在一种用于感测的方法中，计数电路产生计数输出和转换计数输出。 计数输出被转换成时变电压，该电压偏置耦合到被感测的存储器单元的字线。 每个存储器单元的目标数据被存储在与该特定存储器单元相关联的数据高速缓存器中。 当检测到存储器单元已经接通时，将与指示存储器单元接通的电压电平的计数输出相关联的转换计数输出与目标数据进行比较。 比较确定存储单元的状态。

    ACCESS LINE DEPENDENT BIASING SCHEMES
    9.
    发明申请
    ACCESS LINE DEPENDENT BIASING SCHEMES 有权
    访问线相关偏移计划

    公开(公告)号：US20130135935A1

    公开(公告)日：2013-05-30

    申请号：US13746114

    申请日：2013-01-21

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Dzung H. Nguyen

    IPC: G11C16/04

    CPC classification number: G11C16/04 ,  G11C8/08 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/08

    Abstract: The present disclosure includes methods, devices, and systems for access line biasing. One embodiment includes selecting, using a controller external to the memory device, a particular access line dependent biasing scheme and corresponding bias conditions for use in performing an access operation on an array of memory cells of the memory device, and performing the access operation using the selected particular access line dependent biasing scheme and corresponding bias conditions. In one or more embodiments, the selected particular access line dependent biasing scheme and corresponding bias conditions is selected by the controller external to the memory device based, at least partially, on a target access line of the array.

    Abstract translation: 本公开包括用于接入线偏置的方法，设备和系统。 一个实施例包括：使用存储器设备外部的控制器选择特定的访问线路依赖偏置方案和相应的偏置条件，以用于对存储器件的存储器单元阵列执行访问操作，以及使用 所选择的特定接入线相关偏置方案和相应的偏置条件。 在一个或多个实施例中，所选择的特定访问线路依赖偏置方案和对应的偏置条件由存储器设备外部的至少部分地基于阵列的目标访问线路选择。

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