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    MEMORY ARRAY PLANE SELECT
    1.
    发明申请
    MEMORY ARRAY PLANE SELECT 有权
    内存阵列选择

    公开(公告)号：US20150332762A1

    公开(公告)日：2015-11-19

    申请号：US14808385

    申请日：2015-07-24

    Applicant: Micron Technology, Inc

    Inventor： Jong Won Lee ,  Gianpaolo Spadini

    IPC: G11C13/00

    CPC classification number: G11C13/0023 ,  G11C5/025 ,  G11C8/12 ,  G11C11/1653 ,  G11C11/1659 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/71

    Abstract: Memory arrays and methods of forming the same are provided. An example memory array can include at least one plane having a plurality of memory cells arranged in a matrix and a plurality of plane selection devices. Groups of the plurality of memory cells are communicatively coupled to a respective one of a plurality of plane selection devices. A decode logic having elements is formed in a substrate material and communicatively coupled to the plurality of plane selection devices. The plurality of memory cells and the plurality of plane selection devices are not formed in the substrate material.

    Abstract translation: 提供了存储器阵列及其形成方法。 示例性存储器阵列可以包括具有以矩阵形式布置的多个存储单元和多个平面选择装置的至少一个平面。 多个存储器单元的组通信地耦合到多个平面选择装置中的相应一个。 具有元件的解码逻辑形成在衬底材料中并且通信地耦合到多个平面选择装置。 多个存储单元和多个平面选择装置不形成在基板材料中。

    Memory array plane select
    3.
    发明授权
    Memory array plane select 有权

    公开(公告)号：US09514809B2

    公开(公告)日：2016-12-06

    申请号：US14808385

    申请日：2015-07-24

    Applicant: Micron Technology, Inc.

    Inventor： Jong Won Lee ,  Gianpaolo Spadini

    IPC: G11C13/00 ,  G11C5/02 ,  G11C8/12 ,  G11C11/16

    Abstract: Memory arrays and methods of forming the same are provided. An example memory array can include at least one plane having a plurality of memory cells arranged in a matrix and a plurality of plane selection devices. Groups of the plurality of memory cells are communicatively coupled to a respective one of a plurality of plane selection devices. A decode logic having elements is formed in a substrate material and communicatively coupled to the plurality of plane selection devices. The plurality of memory cells and the plurality of plane selection devices are not formed in the substrate material.

    Array Of Memory Cells, Methods Associated With Forming Memory Cells That Comprise Programmable Material, And Methods Associated With Forming Memory Cells That Comprise Selector Device Material
    4.
    发明申请
    Array Of Memory Cells, Methods Associated With Forming Memory Cells That Comprise Programmable Material, And Methods Associated With Forming Memory Cells That Comprise Selector Device Material 审中-公开
    存储单元阵列，与形成可编程材料的存储单元相关联的方法，以及与构成选择器器件材料的形成记忆单元相关联的方法

    公开(公告)号：US20160307963A1

    公开(公告)日：2016-10-20

    申请号：US14690803

    申请日：2015-04-20

    Applicant: Micron Technology, Inc.

    Inventor： Max F. Hineman ,  Jong Won Lee

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2427 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1683

    Abstract: In one embodiment, a method associated with forming a memory cell that comprises programmable material comprises forming a stack comprising sacrificial material over lower conductive material. The sacrificial material is first patterned in a first direction to form a sacrificial line. After the first patterning, second patterning is conducted of the sacrificial material of the sacrificial line in a second direction that crosses the first direction to form a sacrificial elevationally-extending projection from the sacrificial line. The sacrificial projection is replaced with phase change material to form an elevationally-extending projection comprising the phase change material. The phase change material projection is incorporated into one of the programmable material or a selector device component of the memory cell being formed. Other embodiments are disclosed.

    Abstract translation: 在一个实施例中，与形成包括可编程材料的存储器单元相关联的方法包括在下导电材料上形成包括牺牲材料的叠层。 牺牲材料首先在第一方向上图案化以形成牺牲线。 在第一图案化之后，在与第一方向交叉的第二方向上对牺牲线的牺牲材料进行第二图案化以从牺牲线形成牺牲垂直延伸的突起。 牺牲突起被相变材料代替以形成包括相变材料的正视延伸突起。 相变材料投影被并入正在形成的存储器单元的可编程材料或选择器件组件之一中。 公开了其他实施例。

    Memory array plane select
    7.
    发明授权
    Memory array plane select 有权
    内存阵列平面选择

    公开(公告)号：US09543003B2

    公开(公告)日：2017-01-10

    申请号：US14808385

    申请日：2015-07-24

    Applicant: Micron Technology, Inc.

    Inventor： Jong Won Lee ,  Gianpaolo Spadini

    IPC: G11C13/00 ,  G11C5/02 ,  G11C8/12 ,  G11C11/16

    CPC classification number: G11C13/0023 ,  G11C5/025 ,  G11C8/12 ,  G11C11/1653 ,  G11C11/1659 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/71

    Abstract: Memory arrays and methods of forming the same are provided. An example memory array can include at least one plane having a plurality of memory cells arranged in a matrix and a plurality of plane selection devices. Groups of the plurality of memory cells are communicatively coupled to a respective one of a plurality of plane selection devices. A decode logic having elements is formed in a substrate material and communicatively coupled to the plurality of plane selection devices. The plurality of memory cells and the plurality of plane selection devices are not formed in the substrate material.

    Abstract translation: 提供了存储器阵列及其形成方法。 示例性存储器阵列可以包括具有以矩阵形式布置的多个存储单元和多个平面选择装置的至少一个平面。 多个存储器单元的组通信地耦合到多个平面选择装置中的相应一个。 具有元件的解码逻辑形成在衬底材料中并且通信地耦合到多个平面选择装置。 多个存储单元和多个平面选择装置不形成在基板材料中。

    MATERIAL TEST STRUCTURE
    8.
    发明申请
    MATERIAL TEST STRUCTURE 有权
    材料试验结构

    公开(公告)号：US20150160146A1

    公开(公告)日：2015-06-11

    申请号：US14596406

    申请日：2015-01-14

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Innocenzo Tortorelli ,  Christina Papagianni ,  Gianpaolo Spadini ,  Jong Won Lee

    IPC: G01N27/04

    CPC classification number: G01N27/04 ,  H01L22/34 ,  H01L43/10 ,  H01L45/04 ,  H01L45/06 ,  H01L45/14 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

    Abstract: Material test structures having cantilever portions and methods of forming the same are described herein. As an example, a method of forming a material test structure includes forming a number of electrode portions in a first dielectric material, forming a second dielectric material on the first dielectric material, wherein the second dielectric material includes a first cantilever portion and a second cantilever portion, and forming a test material on the number of electrode portions, the first dielectric material, and the second dielectric material.

    Abstract translation: 本文描述了具有悬臂部分的材料测试结构及其形成方法。 作为示例，形成材料测试结构的方法包括在第一介电材料中形成多个电极部分，在第一电介质材料上形成第二电介质材料，其中第二电介质材料包括第一悬臂部分和第二悬臂 并且在电极部分，第一介电材料和第二介电材料的数量上形成测试材料。

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