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Patent Agency Ranking
1.发明授权Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines 有权与具有单独选择线的电阻式存储单元阵列相关联的装置和操作方法公开(公告)号：US09378818B2
公开(公告)日：2016-06-28
申请号：US14185095
申请日：2014-02-20
Applicant: Micron Technology, Inc.
Inventor： Zengtao T. Liu , Kirk D. Prall , Mike Violette
CPC classification number: H01L27/2436 , G11C5/063 , G11C8/14 , G11C11/56 , G11C13/0002 , G11C13/0021 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2213/74 , G11C2213/78 , G11C2213/79 , H01L27/222 , H01L27/228 , H01L27/24 , H01L27/2463 , H01L43/08 , H01L43/10 , H01L45/065 , H01L45/085 , H01L45/141 , H01L45/146 , H01L45/147
Abstract: The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data line and including a first resistive storage element and a first access device, a second memory cell coupled to the data line and including a second resistive storage element and a second access device, an isolation device formed between the first access device and the second access device, a first select line coupled to the first resistive storage element, and a second select line coupled to the second resistive storage element, wherein the second select line is separate from the first select line.
Abstract translation: 本公开包括包括电阻性存储器的方法和装置。 多个实施例包括耦合到数据线并包括第一电阻存储元件和第一存取器件的第一存储器单元，耦合到数据线并包括第二电阻存储元件和第二存取器件的第二存储单元， 形成在第一存取装置和第二存取装置之间的隔离装置，耦合到第一电阻存储元件的第一选择线和耦合到第二电阻存储元件的第二选择线，其中第二选择线与第一选择线分开 线。
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2.发明申请APPARATUSES AND OPERATION METHODS ASSOCIATED WITH RESISTIVE MEMORY CELL ARRAYS WITH SEPARATE SELECT LINES 有权与具有独立选择线的电阻记忆体阵列相关的装置和操作方法公开(公告)号：US20140233300A1
公开(公告)日：2014-08-21
申请号：US14185095
申请日：2014-02-20
Applicant: Micron Technology, Inc.
Inventor： Zengtao T. Liu , Kirk D. Prall , Mike Violette
IPC: G11C13/00
CPC classification number: H01L27/2436 , G11C5/063 , G11C8/14 , G11C11/56 , G11C13/0002 , G11C13/0021 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2213/74 , G11C2213/78 , G11C2213/79 , H01L27/222 , H01L27/228 , H01L27/24 , H01L27/2463 , H01L43/08 , H01L43/10 , H01L45/065 , H01L45/085 , H01L45/141 , H01L45/146 , H01L45/147
Abstract: The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data line and including a first resistive storage element and a first access device, a second memory cell coupled to the data line and including a second resistive storage element and a second access device, an isolation device formed between the first access device and the second access device, a first select line coupled to the first resistive storage element, and a second select line coupled to the second resistive storage element, wherein the second select line is separate from the first select line.
Abstract translation: 本公开包括包括电阻性存储器的方法和装置。 多个实施例包括耦合到数据线并包括第一电阻存储元件和第一存取器件的第一存储器单元，耦合到数据线并包括第二电阻存储元件和第二存取器件的第二存储单元， 形成在第一存取装置和第二存取装置之间的隔离装置，耦合到第一电阻存储元件的第一选择线和耦合到第二电阻存储元件的第二选择线，其中第二选择线与第一选择线分开 线。
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3.发明授权Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines 有权与具有单独选择线的电阻式存储单元阵列相关联的装置和操作方法公开(公告)号：US09548335B2
公开(公告)日：2017-01-17
申请号：US15171890
申请日：2016-06-02
Applicant: Micron Technology, Inc.
Inventor： Zengtao T. Liu , Kirk D. Prall , Mike Violette
CPC classification number: H01L27/2436 , G11C5/063 , G11C8/14 , G11C11/56 , G11C13/0002 , G11C13/0021 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2213/74 , G11C2213/78 , G11C2213/79 , H01L27/222 , H01L27/228 , H01L27/24 , H01L27/2463 , H01L43/08 , H01L43/10 , H01L45/065 , H01L45/085 , H01L45/141 , H01L45/146 , H01L45/147
Abstract: The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data line and including a first resistive storage element and a first access device, a second memory cell coupled to the data line and including a second resistive storage element and a second access device, an isolation device formed between the first access device and the second access device, a first select line coupled to the first resistive storage element, and a second select line coupled to the second resistive storage element, wherein the second select line is separate from the first select line.
Abstract translation: 本公开包括包括电阻性存储器的方法和装置。 多个实施例包括耦合到数据线并包括第一电阻存储元件和第一存取器件的第一存储器单元，耦合到数据线并包括第二电阻存储元件和第二存取器件的第二存储单元， 形成在第一存取装置和第二存取装置之间的隔离装置，耦合到第一电阻存储元件的第一选择线和耦合到第二电阻存储元件的第二选择线，其中第二选择线与第一选择线分开 线。
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公开(公告)号：US20160276409A1
公开(公告)日：2016-09-22
申请号：US15171890
申请日：2016-06-02
Applicant: Micron Technology, Inc.
Inventor： Zengtao T. Liu , Kirk D. Prall , Mike Violette
CPC classification number: H01L27/2436 , G11C5/063 , G11C8/14 , G11C11/56 , G11C13/0002 , G11C13/0021 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2213/74 , G11C2213/78 , G11C2213/79 , H01L27/222 , H01L27/228 , H01L27/24 , H01L27/2463 , H01L43/08 , H01L43/10 , H01L45/065 , H01L45/085 , H01L45/141 , H01L45/146 , H01L45/147
Abstract: The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data line and including a first resistive storage element and a first access device, a second memory cell coupled to the data line and including a second resistive storage element and a second access device, an isolation device formed between the first access device and the second access device, a first select line coupled to the first resistive storage element, and a second select line coupled to the second resistive storage element, wherein the second select line is separate from the first select line.
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5.发明申请MEMORY ELEMENTS USING SELF-ALIGNED PHASE CHANGE MATERIAL LAYERS AND METHODS OF MANUFACTURING SAME 有权使用自对准相变材料层的记忆元件及其制造方法公开(公告)号：US20130248810A1
公开(公告)日：2013-09-26
申请号：US13889777
申请日：2013-05-08
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jun Liu , Mike Violette , Jon Daley
IPC: H01L45/00
CPC classification number: H01L45/06 , H01L27/2463 , H01L45/124 , H01L45/144 , H01L45/1691
Abstract: A memory element and method of forming the same. The memory element includes a substrate supporting a first electrode, a dielectric layer over the first electrode having a via exposing a portion of the first electrode, a phase change material layer formed over sidewalls of the via and contacting the exposed portion of the first electrode, insulating material formed over the phase change material layer and a second electrode formed over the insulating material and contacting the phase change material layer.
Abstract translation: 记忆元件及其形成方法。 存储元件包括支撑第一电极的基板，在第一电极上的电介质层，具有暴露第一电极的一部分的通孔，形成在通孔的侧壁上并与第一电极的暴露部分接触的相变材料层， 形成在相变材料层上的绝缘材料和形成在绝缘材料上并与相变材料层接触的第二电极。
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