公开(公告)号：US07986000B2

公开(公告)日：2011-07-26

申请号：US12564349

申请日：2009-09-22

申请人： Makoto Mizukami ,  Kiyohito Nishihara ,  Masaki Kondo ,  Takashi Izumida ,  Hirokazu Ishida ,  Atsushi Fukumoto ,  Fumiki Aiso ,  Daigo Ichinose ,  Tadashi Iguchi

发明人： Makoto Mizukami ,  Kiyohito Nishihara ,  Masaki Kondo ,  Takashi Izumida ,  Hirokazu Ishida ,  Atsushi Fukumoto ,  Fumiki Aiso ,  Daigo Ichinose ,  Tadashi Iguchi

IPC分类号： H01L29/76 ,  H01L21/00 ,  H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor device is formed on a SOI substrate having a semiconductor substrate, a buried oxide film formed on the semiconductor substrate, and a semiconductor layer formed on the buried oxide film, the semiconductor substrate having a first conductive type, the semiconductor layer having a second conductive type, wherein the buried oxide film has a first opening opened therethrough for communicating the semiconductor substrate with the semiconductor layer, the semiconductor layer is arranged to have a first buried portion buried in the first opening in contact with the semiconductor substrate and a semiconductor layer main portion positioned on the first buried portion and on the buried oxide film, the semiconductor substrate has a connection layer buried in a surface of the semiconductor substrate and electrically connected to the first buried portion in the first opening, the connection layer having the second conductive type, and the semiconductor device includes a contact electrode buried in a second opening, a side surface of the contact electrode being connected to the semiconductor layer main portion, a bottom surface of the contact electrode being connected to the connection layer, the second opening passing through the semiconductor layer main portion and the buried oxide film, and the second opening reaching a surface portion of the connection layer.

摘要翻译： 半导体器件形成在具有半导体衬底的SOI衬底上，形成在半导体衬底上的掩埋氧化膜以及形成在掩埋氧化膜上的半导体层，该半导体衬底具有第一导电类型，该半导体层具有第二导电型 导电型，其中所述掩埋氧化物膜具有通过其开口的第一开口，用于使所述半导体衬底与所述半导体层连通，所述半导体层被布置为具有埋在所述第一开口中的与所述半导体衬底接触的第一掩埋部分和半导体层 主要部分位于第一掩埋部分和掩埋氧化膜上，半导体衬底具有埋在半导体衬底的表面中并与第一开口中的第一掩埋部分电连接的连接层，连接层具有第二导电 类型，并且半导体器件包括接触电极 阴极埋入第二开口中，接触电极的侧表面连接到半导体层主体部分，接触电极的底表面连接到连接层，第二开口穿过半导体层主体部分和埋设 氧化膜，第二开口到达连接层的表面部分。

公开(公告)号：US20100133627A1

公开(公告)日：2010-06-03

申请号：US12603099

申请日：2009-10-21

申请人： Makoto Mizukami ,  Kiyohito Nishihara

发明人： Makoto Mizukami ,  Kiyohito Nishihara

IPC分类号： H01L27/088

CPC分类号： H01L27/11568 ,  G11C16/0483 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/1203

摘要： A depletion-type NAND flash memory includes a NAND string composed of a plurality of serially connected FETs, a control circuit which controls gate potentials of the plurality of FETs in a read operation, a particular potential storage, and an adjacent memory cell threshold storage, wherein each of the plurality of FETs is a transistor whose threshold changes in accordance with a charge quantity in a charge accumulation layer, the adjacent memory cell threshold storage stores a threshold of a source line side FET adjacent to a source line side of a selected FET, and the control circuit applies a potential to the gate electrode of the source line side FET in the read operation, the applied potential being obtained by adding a particular potential stored in the particular potential storage to a threshold stored in the adjacent memory cell threshold storage.

摘要翻译： 耗尽型NAND闪存包括由多个串联连接的FET组成的NAND串，控制电路，其在读取操作中控制多个FET的栅极电位，特定的电位存储器和相邻的存储单元阈值存储器， 其中，所述多个FET中的每一个是其阈值根据电荷累积层中的电荷量而变化的晶体管，所述相邻存储单元阈值存储器存储与所选择的FET的源极侧相邻的源极侧FET的阈值 ，并且控制电路在读取操作中向源极侧FET的栅电极施加电位，所施加的电位通过将存储在特定电位存储器中的特定电位加到存储在相​​邻存储单元阈值存储器中的阈值 。

公开(公告)号：US20100117135A1

公开(公告)日：2010-05-13

申请号：US12564349

申请日：2009-09-22

申请人： Makoto MIZUKAMI ,  Kiyohito Nishihara ,  Masaki Kondo ,  Takashi Izumida ,  Hirokazu Ishida ,  Atsushi Fukumoto ,  Fumiki Aiso ,  Daigo Ichinose ,  Tadashi Iguchi

发明人： Makoto MIZUKAMI ,  Kiyohito Nishihara ,  Masaki Kondo ,  Takashi Izumida ,  Hirokazu Ishida ,  Atsushi Fukumoto ,  Fumiki Aiso ,  Daigo Ichinose ,  Tadashi Iguchi

IPC分类号： H01L27/12 ,  H01L21/86

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor device is formed on a SOI substrate having a semiconductor substrate, a buried oxide film formed on the semiconductor substrate, and a semiconductor layer formed on the buried oxide film, the semiconductor substrate having a first conductive type, the semiconductor layer having a second conductive type, wherein the buried oxide film has a first opening opened therethrough for communicating the semiconductor substrate with the semiconductor layer, the semiconductor layer is arranged to have a first buried portion buried in the first opening in contact with the semiconductor substrate and a semiconductor layer main portion positioned on the first buried portion and on the buried oxide film, the semiconductor substrate has a connection layer buried in a surface of the semiconductor substrate and electrically connected to the first buried portion in the first opening, the connection layer having the second conductive type, and the semiconductor device includes a contact electrode buried in a second opening, a side surface of the contact electrode being connected to the semiconductor layer main portion, a bottom surface of the contact electrode being connected to the connection layer, the second opening passing through the semiconductor layer main portion and the buried oxide film, and the second opening reaching a surface portion of the connection layer.

摘要翻译： 半导体器件形成在具有半导体衬底的SOI衬底上，形成在半导体衬底上的掩埋氧化膜以及形成在掩埋氧化膜上的半导体层，该半导体衬底具有第一导电类型，该半导体层具有第二导电型 导电型，其中所述掩埋氧化物膜具有通过其开口的第一开口，用于使所述半导体衬底与所述半导体层连通，所述半导体层被布置为具有埋在所述第一开口中的与所述半导体衬底接触的第一掩埋部分和半导体层 主要部分位于第一掩埋部分和掩埋氧化膜上，半导体衬底具有埋在半导体衬底的表面中并与第一开口中的第一掩埋部分电连接的连接层，连接层具有第二导电 类型，并且半导体器件包括接触电极 阴极埋入第二开口中，接触电极的侧表面连接到半导体层主体部分，接触电极的底表面连接到连接层，第二开口穿过半导体层主体部分和埋设 氧化膜，第二开口到达连接层的表面部分。

公开(公告)号：US08183624B2

公开(公告)日：2012-05-22

申请号：US12061075

申请日：2008-04-02

申请人： Makoto Mizukami ,  Kiyohito Nishihara

发明人： Makoto Mizukami ,  Kiyohito Nishihara

IPC分类号： H01L29/788

CPC分类号： H01L27/105 ,  H01L27/0688 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11556

摘要： A semiconductor memory device includes a substrate having a step including a first upper surface and a second upper surface higher than the first upper surface, a memory cell array formed on the first upper surface, and a peripheral circuit formed on the second upper surface and configured to supply an electrical signal to the memory cell array. The memory cell array includes a stacked structure having a plurality of first interconnection layers and a plurality of second interconnection layers respectively connected to the first interconnection layers. The first interconnection layers are stacked on the first upper surface, are separated from each other by insulating films, and extend in a first direction. The second interconnection layers extend upward and are separated from each other by insulating films.

摘要翻译： 半导体存储器件包括具有包括第一上表面和高于第一上表面的第二上表面的步骤的衬底，形成在第一上表面上的存储单元阵列和形成在第二上表面上的外围电路， 以向存储单元阵列提供电信号。 存储单元阵列包括具有分别连接到第一互连层的多个第一互连层和多个第二互连层的层叠结构。 第一互连层堆叠在第一上表面上，通过绝缘膜彼此分离，并沿第一方向延伸。 第二互连层向上延伸并通过绝缘膜彼此分离。

公开(公告)号：US08039886B2

公开(公告)日：2011-10-18

申请号：US12603099

申请日：2009-10-21

申请人： Makoto Mizukami ,  Kiyohito Nishihara

发明人： Makoto Mizukami ,  Kiyohito Nishihara

IPC分类号： H01L29/94

CPC分类号： H01L27/11568 ,  G11C16/0483 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/1203

摘要： A depletion-type NAND flash memory includes a NAND string composed of a plurality of serially connected FETs, a control circuit which controls gate potentials of the plurality of FETs in a read operation, a particular potential storage, and an adjacent memory cell threshold storage, wherein each of the plurality of FETs is a transistor whose threshold changes in accordance with a charge quantity in a charge accumulation layer, the adjacent memory cell threshold storage stores a threshold of a source line side FET adjacent to a source line side of a selected FET, and the control circuit applies a potential to the gate electrode of the source line side FET in the read operation, the applied potential being obtained by adding a particular potential stored in the particular potential storage to a threshold stored in the adjacent memory cell threshold storage.

摘要翻译： 耗尽型NAND闪存包括由多个串联连接的FET组成的NAND串，控制电路，其在读取操作中控制多个FET的栅极电位，特定的电位存储器和相邻的存储单元阈值存储器， 其中，所述多个FET中的每一个是其阈值根据电荷累积层中的电荷量而变化的晶体管，所述相邻存储单元阈值存储器存储与所选择的FET的源极侧相邻的源极侧FET的阈值 ，并且控制电路在读取操作中向源极侧FET的栅电极施加电位，所施加的电位通过将存储在特定电位存储器中的特定电位加到存储在相​​邻存储单元阈值存储器中的阈值 。

公开(公告)号：US20080253183A1

公开(公告)日：2008-10-16

申请号：US12061075

申请日：2008-04-02

申请人： Makoto Mizukami ,  Kiyohito Nishihara

发明人： Makoto Mizukami ,  Kiyohito Nishihara

IPC分类号： G11C16/04

CPC分类号： H01L27/105 ,  H01L27/0688 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11556

摘要： A semiconductor memory device includes a substrate having a step including a first upper surface and a second upper surface higher than the first upper surface, a memory cell array formed on the first upper surface, and a peripheral circuit formed on the second upper surface and configured to supply an electrical signal to the memory cell array. The memory cell array includes a stacked structure having a plurality of first interconnection layers and a plurality of second interconnection layers respectively connected to the first interconnection layers. The first interconnection layers are stacked on the first upper surface, are separated from each other by insulating films, and extend in a first direction. The second interconnection layers extend upward and are separated from each other by insulating films.

摘要翻译： 半导体存储器件包括具有包括第一上表面和高于第一上表面的第二上表面的步骤的衬底，形成在第一上表面上的存储单元阵列和形成在第二上表面上的外围电路， 以向存储单元阵列提供电信号。 存储单元阵列包括具有分别连接到第一互连层的多个第一互连层和多个第二互连层的层叠结构。 第一互连层堆叠在第一上表面上，通过绝缘膜彼此分离，并沿第一方向延伸。 第二互连层向上延伸并且通过绝缘膜彼此分离。

公开(公告)号：US08344441B2

公开(公告)日：2013-01-01

申请号：US12839723

申请日：2010-07-20

申请人： Kiyohito Nishihara

发明人： Kiyohito Nishihara

IPC分类号： H01L29/788

CPC分类号： H01L21/76819 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11568

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes: a semiconductor substrate; an element isolation insulator formed in an upper portion of the semiconductor substrate and dividing the upper portion into first and second active areas extending in a first direction; a first contact connected to the first active area; and a second contact connected to the second active area. Each of the first and second active area includes: a first portion connected to one of the first contact and the second contact; and a second portion having an upper surface being placed lower than an upper surface of the first portion. The first contact and the second contact are mutually shifted in the first direction. The first portion of the first active area is disposed adjacent to the second portion of the second active area.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括：半导体衬底; 形成在所述半导体衬底的上部并将所述上部分割成沿第一方向延伸的第一和第二有源区的元件绝缘绝缘体; 连接到第一活动区域的第一触点; 以及连接到第二活动区域的第二触点。 第一和第二有效区域中的每一个包括：连接到第一接触件和第二接触件之一的第一部件; 以及第二部分，其具有比第一部分的上表面低的上表面。 第一触点和第二触点在第一方向相互移位。 第一有效区域的第一部分被布置成与第二有效区域的第二部分相邻。

公开(公告)号：US20120018780A1

公开(公告)日：2012-01-26

申请号：US13075665

申请日：2011-03-30

申请人： Kazuaki Iwasawa ,  Shigeo Kondo ,  Hiroshi Akahori ,  Kiyohito Nishihara ,  Yingkang Zhang ,  Masaki Kondo ,  Hidenobu Nagashima ,  Takashi Ichikawa

发明人： Kazuaki Iwasawa ,  Shigeo Kondo ,  Hiroshi Akahori ,  Kiyohito Nishihara ,  Yingkang Zhang ,  Masaki Kondo ,  Hidenobu Nagashima ,  Takashi Ichikawa

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L27/11521

摘要： According to one embodiment, a method is disclosed for manufacturing a semiconductor device. A side face parallel to a channel direction of a plurality of gate electrodes provided via a gate insulating film above a semiconductor substrate is included as a part of an inner wall of an isolation groove provided between the adjacent gate electrodes. The method can include forming a protection film covering the side face of the gate electrode. The method can include etching the semiconductor substrate using the gate electrode as a mask to form the isolation groove. The side face of the gate electrode is covered with the protection film. The method can include forming a first insulating film by oxidizing a surface of the isolation groove to fill a bottom portion of the isolation groove. In addition, the method can include forming a second insulating film on the first insulating film to fill an upper portion of the isolation groove including the side face of the gate electrode.

摘要翻译： 根据一个实施例，公开了一种用于制造半导体器件的方法。 作为设置在相邻栅电极之间的隔离槽的内壁的一部分，包括平行于通过半导体基板上方的栅极绝缘膜设置的多个栅电极的沟道方向的侧面。 该方法可以包括形成覆盖栅电极的侧面的保护膜。 该方法可以包括使用栅电极作为掩模来蚀刻半导体衬底以形成隔离槽。 栅电极的侧面被保护膜覆盖。 该方法可以包括通过氧化隔离槽的表面来填充隔离槽的底部来形成第一绝缘膜。 此外，该方法可以包括在第一绝缘膜上形成第二绝缘膜以填充包括栅电极的侧面的隔离槽的上部。

公开(公告)号：US07928516B2

公开(公告)日：2011-04-19

申请号：US12276815

申请日：2008-11-24

申请人： Kiyohito Nishihara

发明人： Kiyohito Nishihara

IPC分类号： H01L29/76

CPC分类号： H01L21/84 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203

摘要： A semiconductor storage device include a semiconductor substrate, an insulating layer provided on the semiconductor substrate and having an opening, a semiconductor layer provided on the insulating layer, the semiconductor layer having a recess at a center of a surface thereof above the opening, a memory cell unit provided on the semiconductor layer and including a plurality of memory cells, current paths of the memory cells being connected in series, a selecting transistor adjacent to the memory cell unit and arranged on a region of the semiconductor layer including the recess, the selecting transistor including a gate insulating film provided on the region of the semiconductor layer including the recess and a gate electrode provided on the gate insulating film.

摘要翻译： 半导体存储装置包括半导体基板，设置在半导体基板上的具有开口的绝缘层，设置在绝缘层上的半导体层，半导体层在开口上方的表面的中心具有凹部，存储器 单元单元，设置在所述半导体层上并且包括多个存储单元，所述存储单元的电流路径串联连接，所述选择晶体管与所述存储单元单元相邻并且布置在包括所述凹部的所述半导体层的区域上，所述选择 晶体管，其包括设置在包括凹部的半导体层的区域上的栅极绝缘膜和设置在栅极绝缘膜上的栅电极。

公开(公告)号：US20070177431A1

公开(公告)日：2007-08-02

申请号：US11447963

申请日：2006-06-07

申请人： Yasuhiko Matsunaga ,  Fumitaka Arai ,  Atsuhiro Sato ,  Makoto Sakuma ,  Masato Endo ,  Kiyohito Nishihara ,  Keiji Shuto ,  Naohisa Iino

发明人： Yasuhiko Matsunaga ,  Fumitaka Arai ,  Atsuhiro Sato ,  Makoto Sakuma ,  Masato Endo ,  Kiyohito Nishihara ,  Keiji Shuto ,  Naohisa Iino

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/3427

摘要： There is disclosed a semiconductor integrated circuit device including a memory cell array having a plurality of blocks, a first non-volatile semiconductor memory cell which is arranged in the memory cell array and has an electric charge storage layer, and a second non-volatile semiconductor memory cell which is arranged in the memory cell array to be adjacent to the first non-volatile semiconductor memory cell and has an electric charge storage layer. Regular data writing is performed with respect to the second non-volatile semiconductor memory cell after regular data writing is carried out with respect to the first non-volatile semiconductor memory cell. Additional data writing is performed with respect to the first non-volatile semiconductor memory cell after regular data writing is carried out with respect to the second non-volatile semiconductor memory cell.

摘要翻译： 公开了一种包括具有多个块的存储单元阵列的半导体集成电路器件，布置在存储单元阵列中并具有电荷存储层的第一非易失性半导体存储单元和第二非易失性半导体 存储单元，布置在与第一非易失性半导体存储单元相邻的存储单元阵列中，并具有电荷存储层。 在相对于第一非易失性半导体存储单元执行常规数据写入之后，相对于第二非易失性半导体存储单元执行正常数据写入。 在相对于第二非易失性半导体存储单元执行常规数据写入之后，相对于第一非易失性半导体存储单元执行附加数据写入。