公开(公告)号：US20080253183A1

公开(公告)日：2008-10-16

申请号：US12061075

申请日：2008-04-02

申请人： Makoto Mizukami ,  Kiyohito Nishihara

发明人： Makoto Mizukami ,  Kiyohito Nishihara

IPC分类号： G11C16/04

CPC分类号： H01L27/105 ,  H01L27/0688 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11556

摘要： A semiconductor memory device includes a substrate having a step including a first upper surface and a second upper surface higher than the first upper surface, a memory cell array formed on the first upper surface, and a peripheral circuit formed on the second upper surface and configured to supply an electrical signal to the memory cell array. The memory cell array includes a stacked structure having a plurality of first interconnection layers and a plurality of second interconnection layers respectively connected to the first interconnection layers. The first interconnection layers are stacked on the first upper surface, are separated from each other by insulating films, and extend in a first direction. The second interconnection layers extend upward and are separated from each other by insulating films.

摘要翻译： 半导体存储器件包括具有包括第一上表面和高于第一上表面的第二上表面的步骤的衬底，形成在第一上表面上的存储单元阵列和形成在第二上表面上的外围电路， 以向存储单元阵列提供电信号。 存储单元阵列包括具有分别连接到第一互连层的多个第一互连层和多个第二互连层的层叠结构。 第一互连层堆叠在第一上表面上，通过绝缘膜彼此分离，并沿第一方向延伸。 第二互连层向上延伸并且通过绝缘膜彼此分离。

公开(公告)号：US20100133627A1

公开(公告)日：2010-06-03

申请号：US12603099

申请日：2009-10-21

申请人： Makoto Mizukami ,  Kiyohito Nishihara

发明人： Makoto Mizukami ,  Kiyohito Nishihara

IPC分类号： H01L27/088

CPC分类号： H01L27/11568 ,  G11C16/0483 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/1203

摘要： A depletion-type NAND flash memory includes a NAND string composed of a plurality of serially connected FETs, a control circuit which controls gate potentials of the plurality of FETs in a read operation, a particular potential storage, and an adjacent memory cell threshold storage, wherein each of the plurality of FETs is a transistor whose threshold changes in accordance with a charge quantity in a charge accumulation layer, the adjacent memory cell threshold storage stores a threshold of a source line side FET adjacent to a source line side of a selected FET, and the control circuit applies a potential to the gate electrode of the source line side FET in the read operation, the applied potential being obtained by adding a particular potential stored in the particular potential storage to a threshold stored in the adjacent memory cell threshold storage.

摘要翻译： 耗尽型NAND闪存包括由多个串联连接的FET组成的NAND串，控制电路，其在读取操作中控制多个FET的栅极电位，特定的电位存储器和相邻的存储单元阈值存储器， 其中，所述多个FET中的每一个是其阈值根据电荷累积层中的电荷量而变化的晶体管，所述相邻存储单元阈值存储器存储与所选择的FET的源极侧相邻的源极侧FET的阈值 ，并且控制电路在读取操作中向源极侧FET的栅电极施加电位，所施加的电位通过将存储在特定电位存储器中的特定电位加到存储在相​​邻存储单元阈值存储器中的阈值 。

公开(公告)号：US07986000B2

公开(公告)日：2011-07-26

申请号：US12564349

申请日：2009-09-22

申请人： Makoto Mizukami ,  Kiyohito Nishihara ,  Masaki Kondo ,  Takashi Izumida ,  Hirokazu Ishida ,  Atsushi Fukumoto ,  Fumiki Aiso ,  Daigo Ichinose ,  Tadashi Iguchi

发明人： Makoto Mizukami ,  Kiyohito Nishihara ,  Masaki Kondo ,  Takashi Izumida ,  Hirokazu Ishida ,  Atsushi Fukumoto ,  Fumiki Aiso ,  Daigo Ichinose ,  Tadashi Iguchi

IPC分类号： H01L29/76 ,  H01L21/00 ,  H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor device is formed on a SOI substrate having a semiconductor substrate, a buried oxide film formed on the semiconductor substrate, and a semiconductor layer formed on the buried oxide film, the semiconductor substrate having a first conductive type, the semiconductor layer having a second conductive type, wherein the buried oxide film has a first opening opened therethrough for communicating the semiconductor substrate with the semiconductor layer, the semiconductor layer is arranged to have a first buried portion buried in the first opening in contact with the semiconductor substrate and a semiconductor layer main portion positioned on the first buried portion and on the buried oxide film, the semiconductor substrate has a connection layer buried in a surface of the semiconductor substrate and electrically connected to the first buried portion in the first opening, the connection layer having the second conductive type, and the semiconductor device includes a contact electrode buried in a second opening, a side surface of the contact electrode being connected to the semiconductor layer main portion, a bottom surface of the contact electrode being connected to the connection layer, the second opening passing through the semiconductor layer main portion and the buried oxide film, and the second opening reaching a surface portion of the connection layer.

摘要翻译： 半导体器件形成在具有半导体衬底的SOI衬底上，形成在半导体衬底上的掩埋氧化膜以及形成在掩埋氧化膜上的半导体层，该半导体衬底具有第一导电类型，该半导体层具有第二导电型 导电型，其中所述掩埋氧化物膜具有通过其开口的第一开口，用于使所述半导体衬底与所述半导体层连通，所述半导体层被布置为具有埋在所述第一开口中的与所述半导体衬底接触的第一掩埋部分和半导体层 主要部分位于第一掩埋部分和掩埋氧化膜上，半导体衬底具有埋在半导体衬底的表面中并与第一开口中的第一掩埋部分电连接的连接层，连接层具有第二导电 类型，并且半导体器件包括接触电极 阴极埋入第二开口中，接触电极的侧表面连接到半导体层主体部分，接触电极的底表面连接到连接层，第二开口穿过半导体层主体部分和埋设 氧化膜，第二开口到达连接层的表面部分。

公开(公告)号：US08183624B2

公开(公告)日：2012-05-22

申请号：US12061075

申请日：2008-04-02

申请人： Makoto Mizukami ,  Kiyohito Nishihara

发明人： Makoto Mizukami ,  Kiyohito Nishihara

IPC分类号： H01L29/788

CPC分类号： H01L27/105 ,  H01L27/0688 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11556

摘要： A semiconductor memory device includes a substrate having a step including a first upper surface and a second upper surface higher than the first upper surface, a memory cell array formed on the first upper surface, and a peripheral circuit formed on the second upper surface and configured to supply an electrical signal to the memory cell array. The memory cell array includes a stacked structure having a plurality of first interconnection layers and a plurality of second interconnection layers respectively connected to the first interconnection layers. The first interconnection layers are stacked on the first upper surface, are separated from each other by insulating films, and extend in a first direction. The second interconnection layers extend upward and are separated from each other by insulating films.

摘要翻译： 半导体存储器件包括具有包括第一上表面和高于第一上表面的第二上表面的步骤的衬底，形成在第一上表面上的存储单元阵列和形成在第二上表面上的外围电路， 以向存储单元阵列提供电信号。 存储单元阵列包括具有分别连接到第一互连层的多个第一互连层和多个第二互连层的层叠结构。 第一互连层堆叠在第一上表面上，通过绝缘膜彼此分离，并沿第一方向延伸。 第二互连层向上延伸并通过绝缘膜彼此分离。

公开(公告)号：US08039886B2

公开(公告)日：2011-10-18

申请号：US12603099

申请日：2009-10-21

申请人： Makoto Mizukami ,  Kiyohito Nishihara

发明人： Makoto Mizukami ,  Kiyohito Nishihara

IPC分类号： H01L29/94

CPC分类号： H01L27/11568 ,  G11C16/0483 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/1203

摘要： A depletion-type NAND flash memory includes a NAND string composed of a plurality of serially connected FETs, a control circuit which controls gate potentials of the plurality of FETs in a read operation, a particular potential storage, and an adjacent memory cell threshold storage, wherein each of the plurality of FETs is a transistor whose threshold changes in accordance with a charge quantity in a charge accumulation layer, the adjacent memory cell threshold storage stores a threshold of a source line side FET adjacent to a source line side of a selected FET, and the control circuit applies a potential to the gate electrode of the source line side FET in the read operation, the applied potential being obtained by adding a particular potential stored in the particular potential storage to a threshold stored in the adjacent memory cell threshold storage.

摘要翻译： 耗尽型NAND闪存包括由多个串联连接的FET组成的NAND串，控制电路，其在读取操作中控制多个FET的栅极电位，特定的电位存储器和相邻的存储单元阈值存储器， 其中，所述多个FET中的每一个是其阈值根据电荷累积层中的电荷量而变化的晶体管，所述相邻存储单元阈值存储器存储与所选择的FET的源极侧相邻的源极侧FET的阈值 ，并且控制电路在读取操作中向源极侧FET的栅电极施加电位，所施加的电位通过将存储在特定电位存储器中的特定电位加到存储在相​​邻存储单元阈值存储器中的阈值 。

公开(公告)号：US09029869B2

公开(公告)日：2015-05-12

申请号：US13034264

申请日：2011-02-24

申请人： Hiroshi Kono ,  Takashi Shinohe ,  Chiharu Ota ,  Makoto Mizukami ,  Takuma Suzuki ,  Johji Nishio

发明人： Hiroshi Kono ,  Takashi Shinohe ,  Chiharu Ota ,  Makoto Mizukami ,  Takuma Suzuki ,  Johji Nishio

IPC分类号： H01L29/15 ,  H01L29/739 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/7395 ,  H01L29/1033 ,  H01L29/66333

摘要： One embodiment of a semiconductor device includes: a silicon carbide substrate including first and second principal surfaces; a first-conductive-type silicon carbide layer on the first principal surface; a second-conductive-type first silicon carbide region at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type third silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type fourth silicon carbide region formed between the first silicon carbide region and the second silicon carbide region, and having an impurity concentration higher than that of the first silicon carbide region; a gate insulator; a gate electrode formed on the gate insulator; an inter-layer insulator; a first electrode connected to the second silicon carbide region and the third silicon carbide region; and a second electrode on the second principal surface.

摘要翻译： 半导体器件的一个实施例包括：包含第一和第二主表面的碳化硅衬底; 第一主表面上的第一导电型碳化硅层; 在所述第一碳化硅层的表面处的第二导电型第一碳化硅区域; 在第一碳化硅区域的表面处的第一导电型第二碳化硅区域; 在第一碳化硅区域的表面处的第二导电型第三碳化硅区域; 在第一碳化硅区域和第二碳化硅区域之间形成的杂质浓度高于第一碳化硅区域的第二导电型第四碳化硅区域; 栅极绝缘体; 形成在栅极绝缘体上的栅电极; 层间绝缘体; 连接到所述第二碳化硅区域和所述第三碳化硅区域的第一电极; 和在第二主表面上的第二电极。

公开(公告)号：US08569795B2

公开(公告)日：2013-10-29

申请号：US13217472

申请日：2011-08-25

申请人： Hiroshi Kono ,  Yukio Nakabayashi ,  Takashi Shinohe ,  Makoto Mizukami

发明人： Hiroshi Kono ,  Yukio Nakabayashi ,  Takashi Shinohe ,  Makoto Mizukami

IPC分类号： H01L33/32 ,  H01L29/80 ,  H01L29/16 ,  H01L27/11 ,  H01L27/10

CPC分类号： H01L29/7802 ,  H01L21/049 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/66068 ,  H01L29/7813

摘要： A semiconductor device of an embodiment includes: a silicon carbide substrate including first and second principal surfaces; a first conductive-type first silicon carbide layer provided on the first principal surface of the silicon carbide substrate; a second conductive-type first silicon carbide region formed on a surface of the first silicon carbide layer; a first conductive-type second silicon carbide region formed on a surface of the first silicon carbide region; a second conductive-type third silicon carbide region formed on the surface of the first silicon carbide region; a gate insulating film continuously formed on the surfaces of the first silicon carbide layer, the first silicon carbide region, and the second silicon carbide region; a first electrode formed of silicon carbide formed on the gate insulating film; a second electrode formed on the first electrode; an interlayer insulating film for covering the first and second electrodes; a third electrode electrically connected to the second silicon carbide region and the third silicon carbide region; and a fourth electrode formed on the second principal surface of the silicon carbide substrate.

摘要翻译： 实施例的半导体器件包括：碳化硅衬底，其包括第一和第二主表面; 设置在碳化硅衬底的第一主表面上的第一导电型第一碳化硅层; 形成在所述第一碳化硅层的表面上的第二导电型第一碳化硅区; 形成在所述第一碳化硅区域的表面上的第一导电型第二碳化硅区域; 形成在所述第一碳化硅区域的表面上的第二导电型第三碳化硅区域; 连续形成在所述第一碳化硅层，所述第一碳化硅区域和所述第二碳化硅区域的表面上的栅极绝缘膜; 形成在所述栅极绝缘膜上的由碳化硅形成的第一电极; 形成在第一电极上的第二电极; 用于覆盖第一和第二电极的层间绝缘膜; 电连接到第二碳化硅区域和第三碳化硅区域的第三电极; 以及形成在碳化硅衬底的第二主表面上的第四电极。

公开(公告)号：US08557695B2

公开(公告)日：2013-10-15

申请号：US12974128

申请日：2010-12-21

申请人： Makoto Mizukami ,  Fumitaka Arai

发明人： Makoto Mizukami ,  Fumitaka Arai

IPC分类号： H01L21/28

CPC分类号： H01L27/11578 ,  G11C5/02 ,  G11C16/0483 ,  H01L27/11568 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： According to an aspect of the present invention, there is provided, a nonvolatile semiconductor storage device including: a substrate; a stacked portion that includes a plurality of conductor layers and a plurality of insulation layers alternately stacked on the substrate, at least one layer of the plurality of conductor layers and the plurality of insulation layers forming a marker layer; a charge accumulation film that is formed on an inner surface of a memory plug hole that is formed in the stacked portion from a top surface to a bottom surface thereof; and a semiconductor pillar that is formed inside the memory plug hole through the charge accumulation film.

摘要翻译： 根据本发明的一个方面，提供一种非易失性半导体存储装置，包括：基板; 堆叠部分，其包括多个导体层和交替堆叠在所述基板上的多个绝缘层，所述多个导体层中的至少一层和所述多个绝缘层形成标记层; 电荷累积膜，其形成在从其顶表面到底表面形成在堆叠部分中的存储器插塞孔的内表面上; 以及通过电荷累积膜形成在存储器插塞孔内部的半导体柱。

公开(公告)号：US07804133B2

公开(公告)日：2010-09-28

申请号：US12022382

申请日：2008-01-30

申请人： Takeshi Murata ,  Makoto Mizukami ,  Fumitaka Arai

发明人： Takeshi Murata ,  Makoto Mizukami ,  Fumitaka Arai

IPC分类号： H01L27/115

CPC分类号： H01L27/105 ,  H01L21/84 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/1203

摘要： Semiconductor storage devices in which a plurality of semiconductor element devices having different functions are disposed in the appropriate region of the partial SOI substrate and the interface between each gate insulator and each gate electrode is formed to be the same level, and manufacturing methods thereof are disclosed. According to one aspect, there is provided a semiconductor storage device includes a first semiconductor region provided in a semiconductor substrate including a buried insulator having opening portions, a second semiconductor region without including buried insulator, a plurality of first semiconductor element devices disposed above the buried insulator, a plurality of second semiconductor element devices each disposed in a region including a region above the opening portion of the buried insulator, and a plurality of third semiconductor element devices disposed in the second semiconductor region.

摘要翻译： 其中具有不同功能的多个半导体元件器件设置在部分SOI衬底的适当区域中并且每个栅绝缘体和每个栅电极之间的界面形成为相同水平的半导体存储器件，并且其制造方法被公开 。 根据一个方面，提供一种半导体存储装置，包括设置在包括具有开口部分的埋入式绝缘体的半导体衬底中的第一半导体区域，不包括埋入绝缘体的第二半导体区域，设置在掩埋层上方的多个第一半导体元件器件 绝缘体，多个第二半导体元件器件，每个第二半导体元件器件设置在包括所述埋入绝缘体的开口部分上方的区域的区域中，以及设置在所述第二半导体区域中的多个第三半导体元件器件。

公开(公告)号：US07696559B2

公开(公告)日：2010-04-13

申请号：US11616522

申请日：2006-12-27

申请人： Fumitaka Arai ,  Riichiro Shirota ,  Makoto Mizukami

发明人： Fumitaka Arai ,  Riichiro Shirota ,  Makoto Mizukami

IPC分类号： H01L27/115

CPC分类号： H01L29/792 ,  G11C16/0483 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor memory device includes: a semiconductor substrate, on which an impurity diffusion layer is formed in a cell array area; a gate wiring stack body formed on the cell array area, in which multiple gate wirings are stacked and separated from each other with insulating films; a gate insulating film formed on the side surface of the gate wiring stack body, in which an insulating charge storage layer is contained, pillar-shaped semiconductor layers arranged along the gate wiring stack body, one side surfaces of which are opposed to the gate wiring stack body via the gate insulating film, each pillar-shaped semiconductor layer having the same conductivity type as the impurity diffusion layer; and data lines formed to be in contact with the upper surfaces of the pillar-shaped semiconductor layers and intersect the gate wirings.

摘要翻译： 半导体存储器件包括：在单元阵列区域中形成有杂质扩散层的半导体衬底; 形成在电池阵列区域上的栅极布线堆叠体，其中多个栅极布线彼此堆叠并且用绝缘膜分离; 形成在栅极布线堆叠体的侧表面上的栅极绝缘膜，其中包含绝缘电荷存储层，沿着栅极布线堆叠体布置的柱状半导体层，其一个侧表面与栅极布线相对 堆叠体经由栅极绝缘膜，每个柱状半导体层具有与杂质扩散层相同的导电类型; 以及形成为与柱状半导体层的上表面接触并与栅极布线相交的数据线。