公开(公告)号：US5253197A

公开(公告)日：1993-10-12

申请号：US580464

申请日：1990-09-11

申请人： Makoto Suzuki ,  Suguru Tachibana ,  Hisayuki Higuchi ,  Katsuhiro Shimohigashi ,  Takehisa Hayashi ,  Makoto Hanawa ,  Tadahiko Nishimukai

发明人： Makoto Suzuki ,  Suguru Tachibana ,  Hisayuki Higuchi ,  Katsuhiro Shimohigashi ,  Takehisa Hayashi ,  Makoto Hanawa ,  Tadahiko Nishimukai

IPC分类号： G06F12/08 ,  G06F12/10 ,  G11C15/04

CPC分类号： G11C15/04 ,  G06F12/0895 ,  G06F12/1054 ,  Y02B60/1225

摘要： In a first embodiment of a CAM (Content Addressable Memory) or cache memory of the present invention disclosed herein, comparing information stored in a memory cell with comparison input information is accomplished in a comparison circuit without first converting a readout current from the memory cell into voltage information. In another embodiment, a matching detection between first stored information outputted from a first memory cell array and second stored information outputted from a second memory cell array is accomplished by an integrally formed sensing and matching detection circuit which is characterized as having both sensing and matching detection capabilities. That is, the sensing and matching detection circuit senses both stored information and thereafter detects matching based on a sensing result.

摘要翻译： 在本文公开的本发明的CAM（内容可寻址存储器）或高速缓冲存储器的第一实施例中，将存储在存储单元中的比较信息与比较输入信息进行比较，在比较电路中完成，而无需将来自存储单元的读出电流转换成 电压信息。 在另一个实施例中，从第一存储单元阵列输出的第一存储信息与从第二存储单元阵列输出的第二存储信息之间的匹配检测由一体形成的感测和匹配检测电路来实现，其特征在于具有检测和匹配检测 能力 也就是说，感测和匹配检测电路感测存储的信息，并且此后基于感测结果检测匹配。

公开(公告)号：US5107141A

公开(公告)日：1992-04-21

申请号：US604454

申请日：1990-10-29

申请人： Kazuo Yano ,  Mitsuru Hiraki ,  Hisayuki Higuchi ,  Suguru Tachibana ,  Makoto Suzuki ,  Katsuhiro Shimohigashi

发明人： Kazuo Yano ,  Mitsuru Hiraki ,  Hisayuki Higuchi ,  Suguru Tachibana ,  Makoto Suzuki ,  Katsuhiro Shimohigashi

IPC分类号： H03K19/00 ,  H03K19/013 ,  H03K19/0944

CPC分类号： H03K19/0013 ,  H03K19/0136 ,  H03K19/09448

摘要： An output circuit portion of a BiCMOS logic circuit adapted to operating on a low voltage has an npn transistor Q5 connected between the power source Vcc and an output N6, and has an npn transistor Q6 connected between the output N6 and ground potential GND. The base of the npn transistor Q5 is driven by the drain output of p-channel MOSFETs MP3, MP4, and the base of the npn transistor Q6 is driven by the drain output of p-channel MOSFET QP5. When the power source voltage Vcc drops, the voltage applied between the drain and the source of MOSFET MP5 becomes small by the effect of V.sub.BE of the transistor Q6, but the drain current of the MOSFET MP5 changes little. Therefore, the BiCMOS circuit operates at high speeds (see FIG. 1) even when the power source voltage drops.

摘要翻译： 适用于低电压工作的BiCMOS逻辑电路的输出电路部分具有连接在电源Vcc和输出N6之间的npn晶体管Q5，并具有连接在输出N6和地电位GND之间的npn晶体管Q6。 npn晶体管Q5的基极由p沟道MOSFET MP3，MP4的漏极输出驱动，npn晶体管Q6的基极由p沟道MOSFET QP5的漏极输出驱动。 当电源电压Vcc下降时，通过晶体管Q6的VBE的影响，施加在MOSFET MP5的漏极和源极之间的电压变小，但MOSFET MP5的漏极电流变化较小。 因此，即使当电源电压下降时，BiCMOS电路也以高速工作（参见图1）。

公开(公告)号：US5218567A

公开(公告)日：1993-06-08

申请号：US789003

申请日：1991-11-07

申请人： Makoto Suzuki ,  Suguru Tachibana ,  Hisayuki Higuchi

发明人： Makoto Suzuki ,  Suguru Tachibana ,  Hisayuki Higuchi

IPC分类号： G06F12/08 ,  G06F12/10 ,  G11C15/04

CPC分类号： G06F12/1054 ,  G06F12/0895 ,  G11C15/04

摘要： A cache memory apparatus made up of a memory cell array (300) and a match detection circuit is disclosed. The match detection circuit produces a detection signal related to whether a search data coincides with a data read out of the memory cell array (300). The match detection circuit applies complementary signals (d, d) of the data read from the memory cell array (300) to the bases of bipolar differential transistors (10, 11), the gates of a pair of field effect transistors (16, 17) are supplied with complementary signals (a, a) of the search data, and the bases of a pair of emitter-follower transistors (12, 13) are connected to the collectors of the bipolar differential transistors (10, 11), thereby producing a detection signal (HITO) from the jointly-connected emitters thereof.

摘要翻译： 公开了一种由存储单元阵列（300）和匹配检测电路构成的高速缓存存储装置。 匹配检测电路产生与搜索数据是否与从存储单元阵列（300）读出的数据一致的检测信号。 匹配检测电路将从存储单元阵列（300）读取的数据的互补信号（d，＆amp; upbar＆d）施加到双极差分晶体管（10,11）的基极，一对场效应晶体管（16， 17）被提供有搜索数据的互补信号（a，＆amp; upbar＆a），并且一对射极跟随器晶体管（12,13）的基极连接到双极差分晶体管（10,11）的集电极， 从而从其共同连接的发射器产生检测信号（＆amp; upbar＆amp; H）。

公开(公告)号：US4928265A

公开(公告)日：1990-05-22

申请号：US266148

申请日：1988-11-02

申请人： Hisayuki Higuchi ,  Noriyuki Homma ,  Makoto Suzuki ,  Suguru Tachibana

发明人： Hisayuki Higuchi ,  Noriyuki Homma ,  Makoto Suzuki ,  Suguru Tachibana

IPC分类号： G11C11/416

CPC分类号： G11C11/416

摘要： Considering the dispersion in the access time of semiconductor memories, at least a first and a second memory circuit are connected to the output of a sense amplifier. The output of the sense amplifier is an input to these two memory circuits alternatively at different timings. The data stored in these memory circuits are alternately transferred to a data output circuit. Even when the access time becomes long, the desired sense data can be successively read out from the output of the data output circuit at a short time interval determined by the clock cycle. When the access time becomes short and even when a second data is generated from the output of the sense amplifier at the timing of transferring a first data in the first memory circuit to the data output circuit, the first data held in the first memory circuit is prevented from being renewed by the second data. In this case too, the desired sense data can be successively read out from the output of the data output circuit at a time interval determined by the clock cycle.

摘要翻译： 考虑到半导体存储器的访问时间的偏差，至少第一和第二存储器电路连接到读出放大器的输出。 读出放大器的输出是以不同的定时交替地输入到这两个存储器电路。 存储在这些存储器电路中的数据被交替地传送到数据输出电路。 即使当访问时间变长时，可以在由时钟周期确定的短时间间隔内从数据输出电路的输出端连续地读出期望的感测数据。 当访问时间变短时，即使在将第一存储器电路中的第一数据传送到数据输出电路的定时从读出放大器的输出产生第二数据时，保持在第一存储器电路中的第一数据为 防止第二个数据被更新。 在这种情况下，也可以在由时钟周期确定的时间间隔内从数据输出电路的输出端连续读出期望的检测数据。

公开(公告)号：US06342710B1

公开(公告)日：2002-01-29

申请号：US09521957

申请日：2000-03-09

申请人： Hisayuki Higuchi ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Keijiro Uehara

发明人： Hisayuki Higuchi ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Keijiro Uehara

IPC分类号： H01L2976

CPC分类号： G11C11/5621 ,  G11C15/04

摘要： A semiconductor integrated circuit, particularly a circuit for a high-speed low-power-consumption table look-aside buffer mounted in a microprocessor LSI. The semiconductor integrated circuit is provided with field effect transistors for comparing inputted multibit data signals with stored data and a coincidence-detecting signal line (25) to which current is applied at least while the data signals are compared with stored data. When the data signals coincide with the stored data, the transistors (26) conduct. The number of transistors (26) is equal to that of the inputted data signals. The drains of the transistors (260 are connected in parallel, and the sources are also connected in parallel and supplied with a predetermined voltage. By the integrated circuit, whether or not the inputted data signals coincide with the stored data is detected by detecting the potential of the coincidence-detecting signal line (25) upon a change of the applied current.

摘要翻译： 一种半导体集成电路，特别是用于安装在微处理器LSI中的用于高速低功耗表格旁路缓冲器的电路。 半导体集成电路设置有用于将输入的多位数据信号与存储的数据进行比较的场效应晶体管和至少在数据信号与存储的数据进行比较时施加电流的符合检测信号线（25）。 当数据信号与存储的数据一致时，晶体管（26）导通。 晶体管（26）的数量等于输入的数据信号的数量。 晶体管的漏极（260）并联连接，源极并联连接并以预定电压供电，通过集成电路，通过检测电位来检测输入的数据信号是否与存储的数据一致 的一致检测信号线（25）。

公开(公告)号：US6121646A

公开(公告)日：2000-09-19

申请号：US913407

申请日：1997-12-05

申请人： Hisayuki Higuchi ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Keijiro Uehara

发明人： Hisayuki Higuchi ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Keijiro Uehara

IPC分类号： G11C11/56 ,  G11C15/04 ,  H01L29/76

CPC分类号： G11C11/5621 ,  G11C15/04

摘要： A semiconductor integrated circuit, particularly a circuit for a high-speed low-power-consumption table look-aside buffer mounted in a microprocessor LSI. The semiconductor integrated circuit is provided with field effect transistors for comparing inputted multibit data signals with stored data and a coincidence-detecting signal line (25) to which current is applied at least while the data signals are compared with stored data. When the data signals coincide with the stored data, the transistors (26) conduct. The number of transistors (26) is equal to that of the inputted data signals. The drains of the transistors (260 are connected in parallel, and the sources are also connected in parallel and supplied with a predetermined voltage. By the integrated circuit, whether or not the inputted data signals coincide with the stored data is detected by detecting the potential of the coincidence-detecting signal line (25) upon a change of the applied current.

摘要翻译： PCT No.PCT / JP96 / 00701 Sec。 371 1997年12月5日第 102（e）日期1997年12月5日PCT 1996年3月18日PCT公布。 出版物WO96 / 29705 日期1996年9月26日一种半导体集成电路，特别是用于安装在微处理器LSI中的高速低功耗表格旁路缓冲器的电路。 半导体集成电路设置有用于将输入的多位数据信号与存储的数据进行比较的场效应晶体管和至少在数据信号与存储的数据进行比较时施加电流的符合检测信号线（25）。 当数据信号与存储的数据一致时，晶体管（26）导通。 晶体管（26）的数量等于输入的数据信号的数量。 晶体管的漏极（260）并联连接，源极并联连接并以预定电压供电，通过集成电路，通过检测电位来检测输入的数据信号是否与存储的数据一致 的一致检测信号线（25）。

公开(公告)号：US5907867A

公开(公告)日：1999-05-25

申请号：US657231

申请日：1996-06-03

申请人： Toshinobu Shinbo ,  Suguru Tachibana ,  Susumu Narita ,  Shinichi Yoshioka ,  Koichiro Ishibashi ,  Hisayuki Higuchi ,  Yoshinobu Nakagome ,  Ikuya Kawasaki ,  Saneaki Tamaki

发明人： Toshinobu Shinbo ,  Suguru Tachibana ,  Susumu Narita ,  Shinichi Yoshioka ,  Koichiro Ishibashi ,  Hisayuki Higuchi ,  Yoshinobu Nakagome ,  Ikuya Kawasaki ,  Saneaki Tamaki

IPC分类号： G06F12/10

CPC分类号： G06F12/1027 ,  G06F2212/652 ,  Y02B60/1225

摘要： A semiconductor integrated circuit device such as a data processing device having a set-associative translation look-aside buffer (TLB). A plurality of address arrays each have a second field for storing the value representing a page size. The values read from the second fields are used to change the range of address comparison by comparators. A plurality of data arrays each have a second field for storing a bit position address designating either an intra-page address or a page number following a page size change. The values read from the second fields of the address arrays are used as the basis for second selectors to select either an address in a predetermined location of an externally input virtual address or the address read from each of the second fields of the data arrays. The selected address is output as a physical address.

摘要翻译： 一种半导体集成电路装置，例如具有集相关翻译后备缓冲器（TLB）的数据处理装置。 多个地址阵列各自具有用于存储表示页面大小的值的第二字段。 从第二个字段读取的值用于通过比较器更改地址比较范围。 多个数据阵列各自具有用于存储指定页面大小改变之后的页内地址或页码的位位置地址的第二字段。 从地址阵列的第二个字段读取的值被用作第二选择器选择外部输入的虚拟地址的预定位置的地址或从数据阵列的每个第二场读取的地址的基础。 所选地址作为物理地址输出。

公开(公告)号：US4942555A

公开(公告)日：1990-07-17

申请号：US376865

申请日：1989-07-07

申请人： Hisayuki Higuchi ,  Makoto Suzuki ,  Noriyuki Homma ,  Kiyoo Itoh

发明人： Hisayuki Higuchi ,  Makoto Suzuki ,  Noriyuki Homma ,  Kiyoo Itoh

IPC分类号： G11C11/418 ,  G11C11/419

CPC分类号： G11C11/418 ,  G11C11/419

摘要： A semiconductor memory is provided having high reliability, and which particularly prevents data destruction by rays, and the like. In a semiconductor memory for detecting memory data from the conduction ratio between a transistor of a flip-flop type memory cell connected to selected word line and data line pairs and a load device of the data line, an arrangement is provided for setting the word line voltage to a voltage lower than the sum of the data line voltage and the threshold voltage of a data transfer MOS transistor of the memory cell. The signal read out from the memory cell is then applied through the data line to a differential amplifier using the base or gate of a junction type transistor as its input. Particularly to set the word line voltage to a voltage lower than the sum of the data line voltage and the threshold voltage of the data transfer MOS transistor of the memory cell, a device having high driving capability such as a bipolar transistor is used as the load of the data line. The word line voltage is changed over to two stages so that the data line voltage V.sub.D and the word line voltage V.sub.W satisfy the relation V.sub.W V.sub.D +V.sub.TH in a write cycle (where V.sub.TH is the threshold voltage of NMOS inside the memory cell).

摘要翻译： 提供了具有高可靠性的半导体存储器，并且特别地防止了由于光线的数据破坏等。 在用于根据连接到所选字线的触发器型存储单元的晶体管与数据线对之间的导通率以及数据线的负载装置的导通比来检测存储器数据的半导体存储器中，提供了用于设置字线 电压低于数据线电压和存储单元的数据传输MOS晶体管的阈值电压之和的电压。 从存储单元读出的信号然后通过数据线施加到使用结型晶体管的基极或栅极作为其输入的差分放大器。 特别是为了将字线电压设定为低于数据线电压和存储单元的数据传输MOS晶体管的阈值电压之和的电压，使用诸如双极型晶体管的具有高驱动能力的器件作为负载 的数据线。 字线电压转换为两级，使得数据线电压VD和字线电压VW在读周期中满足关系VW VD + VTH（其中VTH 是存储单元内的NMOS的阈值电压）。

公开(公告)号：US4937480A

公开(公告)日：1990-06-26

申请号：US373263

申请日：1989-06-27

申请人： Hisayuki Higuchi ,  Makoto Suzuki ,  Noriyuki Homma

发明人： Hisayuki Higuchi ,  Makoto Suzuki ,  Noriyuki Homma

IPC分类号： G11C7/12 ,  G11C8/06 ,  G11C8/10 ,  G11C11/418

CPC分类号： G11C8/10 ,  G11C11/418 ,  G11C7/12 ,  G11C8/06

摘要： A semiconductor integrated circuit includes an input buffer circuit, a decoder circuit and a plurality of memory cells. Each of the input buffer circuit and the decoder circuit consists of a combination of bipolar transistors and MOS transistors. In this combination various measures are taken to increase the operation speed and to reduce the electric power consumption. In an example thereof the data line load for the memory cells is constituted by Schottky barrier type diodes. In another example the load used for the respective emitter follower transistors is constituted by an MOS transistor operating as a variable resistance. In still another example, in a CMOS NOR ciruit of the decoder circuit the number of P channel MOS transistors are fewer than the number of N channel MOS transistors.

公开(公告)号：US4858191A

公开(公告)日：1989-08-15

申请号：US131644

申请日：1987-12-11

申请人： Hisayuki Higuchi ,  Makoto Suzuki ,  Noriyuki Homma

发明人： Hisayuki Higuchi ,  Makoto Suzuki ,  Noriyuki Homma

IPC分类号： G11C7/12 ,  G11C8/06 ,  G11C8/10 ,  G11C11/418

CPC分类号： G11C8/10 ,  G11C11/418 ,  G11C7/12 ,  G11C8/06

摘要： A semiconductor integrated circuit includes an input buffer circuit, a decoder circuit and a plurality of memory cells. Each of the input buffer circuit and the decoder circuit consists of a combination of bipolar transistors and MOS transistors. In this combination various measures are taken to increase the operation speed and to reduce the electric power consumption. In an example thereof the data line load for the memory cells is constituted by Schottky barrier type diodes. In another example the load used for the respective emitter follower transistors is constituted by an MOS transistor operating as a variable resistance.In still another example, in a CMOS NOR circuit of the decoder circuit the number of P channel MOS transistors are fewer than the number of N channel MOS transistors.

摘要翻译： 半导体集成电路包括输入缓冲电路，解码器电路和多个存储单元。 输入缓冲电路和解码电路各自由双极晶体管和MOS晶体管组成。 在这种组合中，采取各种措施来提高操作速度并降低电力消耗。 在其示例中，存储单元的数据线负载由肖特基势垒型二极管构成。 在另一示例中，用于各个射极跟随器晶体管的负载由作为可变电阻工作的MOS晶体管构成。 在另一示例中，在解码器电路的CMOS NOR电路中，P沟道MOS晶体管的数量少于N沟道MOS晶体管的数量。