公开(公告)号：US5253197A

公开(公告)日：1993-10-12

申请号：US580464

申请日：1990-09-11

申请人： Makoto Suzuki ,  Suguru Tachibana ,  Hisayuki Higuchi ,  Katsuhiro Shimohigashi ,  Takehisa Hayashi ,  Makoto Hanawa ,  Tadahiko Nishimukai

发明人： Makoto Suzuki ,  Suguru Tachibana ,  Hisayuki Higuchi ,  Katsuhiro Shimohigashi ,  Takehisa Hayashi ,  Makoto Hanawa ,  Tadahiko Nishimukai

IPC分类号： G06F12/08 ,  G06F12/10 ,  G11C15/04

CPC分类号： G11C15/04 ,  G06F12/0895 ,  G06F12/1054 ,  Y02B60/1225

摘要： In a first embodiment of a CAM (Content Addressable Memory) or cache memory of the present invention disclosed herein, comparing information stored in a memory cell with comparison input information is accomplished in a comparison circuit without first converting a readout current from the memory cell into voltage information. In another embodiment, a matching detection between first stored information outputted from a first memory cell array and second stored information outputted from a second memory cell array is accomplished by an integrally formed sensing and matching detection circuit which is characterized as having both sensing and matching detection capabilities. That is, the sensing and matching detection circuit senses both stored information and thereafter detects matching based on a sensing result.

摘要翻译： 在本文公开的本发明的CAM（内容可寻址存储器）或高速缓冲存储器的第一实施例中，将存储在存储单元中的比较信息与比较输入信息进行比较，在比较电路中完成，而无需将来自存储单元的读出电流转换成 电压信息。 在另一个实施例中，从第一存储单元阵列输出的第一存储信息与从第二存储单元阵列输出的第二存储信息之间的匹配检测由一体形成的感测和匹配检测电路来实现，其特征在于具有检测和匹配检测 能力 也就是说，感测和匹配检测电路感测存储的信息，并且此后基于感测结果检测匹配。

公开(公告)号：US06219738B1

公开(公告)日：2001-04-17

申请号：US09514351

申请日：2000-02-28

申请人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

发明人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

IPC分类号： G06F1300

CPC分类号： G06F13/4027 ,  G06F13/36

摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

公开(公告)号：US6128688A

公开(公告)日：2000-10-03

申请号：US296660

申请日：1999-04-23

申请人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

发明人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

IPC分类号： G06F13/36 ,  G06F3/00 ,  G06F5/00 ,  G06F13/00 ,  G06F13/368 ,  G06F13/40

CPC分类号： G06F13/4027 ,  G06F13/36

摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

公开(公告)号：US06049221A

公开(公告)日：2000-04-11

申请号：US111804

申请日：1998-07-08

申请人： Kenichi Ishibashi ,  Takehisa Hayashi ,  Tsutomu Goto ,  Hideki Murayama ,  Akira Yamagiwa ,  Yasuhiro Ishii ,  Naoki Hamanaka ,  Masabumi Shibata

发明人： Kenichi Ishibashi ,  Takehisa Hayashi ,  Tsutomu Goto ,  Hideki Murayama ,  Akira Yamagiwa ,  Yasuhiro Ishii ,  Naoki Hamanaka ,  Masabumi Shibata

IPC分类号： H03K19/003 ,  H03K19/00 ,  H03K19/0175 ,  H04L25/02 ,  H03K19/175

CPC分类号： H03K19/0005

摘要： A semiconductor integrated circuit system having a function of automatically adjusting an output resistance value with reference to a temperature of an LSI which is operating. When a count value obtained from a counter by counting the output of a timer becomes equal to a predetermined value, a temperature sensor measures temperatures of LSIs. If a temperature fluctuation measured from a previous measured value is greater than a predetermined width, then a control apparatus issues an output resistance value adjustment request signal to output resistance adjustment units of the LSIs. When receiving the output resistance value adjustment request signal, the output resistance value adjustment units stop the signal transmission between the LSIs, adjust output resistance values of output circuits in such a manner that the output resistance values are matched with a characteristic impedance of a transmission line, and maintains the adjusted output resistance values until the output resistance value adjustment units receive next output resistance value adjustment request signal.

摘要翻译： 具有参照正在运行的LSI的温度来自动调整输出电阻值的功能的半导体集成电路系统。 当通过对计时器的输出进行计数而得到的计数值等于预定值时，温度传感器测量LSI的温度。 如果从先前测量值测量的温度波动大于预定宽度，则控制装置发出输出电阻值调整请求信号以输出LSI的电阻调节单元。 当接收到输出电阻值调整请求信号时，输出电阻值调节单元停止LSI之间的信号传输，以输出电阻值与传输线的特性阻抗匹配的方式调整输出电路的输出电阻值 并保持调整后的输出电阻值直到输出电阻值调整单元接收到下一个输出电阻值调整请求信号。

公开(公告)号：US5941973A

公开(公告)日：1999-08-24

申请号：US203621

申请日：1998-12-01

申请人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

发明人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

IPC分类号： G06F13/36 ,  G06F3/00 ,  G06F5/00 ,  G06F13/00 ,  G06F13/368 ,  G06F13/40

CPC分类号： G06F13/4027 ,  G06F13/36

摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

摘要翻译： 在数据处理系统中，连接到其系统总线的多个模块被分配有标识符。 当源模块发起对另一个模块的拆分读取访问时，源模块将发送访问目标模块的地址和源模块的标识符。 当向源模块发送响应时，目的地模块向其返回响应数据和源模块的标识符。 从目标模块检查标识符，源模块确定作为对发起的访问的响应返回的响应数据。

公开(公告)号：US5936955A

公开(公告)日：1999-08-10

申请号：US964712

申请日：1997-11-05

申请人： Takeshi Aimoto ,  Hidenori Inouchi ,  Shoichi Murase ,  Shinichi Tanabe ,  Kazuhiro Hashimoto ,  Hiroshi Iwamoto ,  Hiroshi Ohguro ,  Takehisa Hayashi ,  Haruyuki Nakayama ,  Kenji Nakajima ,  Satoshi Yoshizawa ,  Hideki Murayama

发明人： Takeshi Aimoto ,  Hidenori Inouchi ,  Shoichi Murase ,  Shinichi Tanabe ,  Kazuhiro Hashimoto ,  Hiroshi Iwamoto ,  Hiroshi Ohguro ,  Takehisa Hayashi ,  Haruyuki Nakayama ,  Kenji Nakajima ,  Satoshi Yoshizawa ,  Hideki Murayama

IPC分类号： H04L12/56 ,  H04L29/06 ,  H04L29/08 ,  H04L29/14 ,  H04J3/24

CPC分类号： H04L49/505 ,  H04L12/56 ,  H04L29/06 ,  H04L47/10 ,  H04L47/32 ,  H04L49/253 ,  H04L69/40 ,  H04L49/30 ,  H04L49/555 ,  H04L69/22 ,  H04L69/329

摘要： A data communication system for a computer system in which a plurality of computers are mutually connected includes: a plurality of computers each having an area to store a command to execute a data communication on the basis of it and a buffer area to store data; a switch circuit to mutually selectively connect the plurality of computers; and a transmission permitting component, connected between the switch circuit and one of the plurality of computers, for outputting a signal to permit the data transmission from such one computer to such another computer; a communication component for transmitting the data received from such one computer by outputting the transmission permission signal from the transmission permitting component to such another computer through the switch circuit; a detecting component to detect the occurrence of an abnormality regarding the data communication from such one computer to such another computer; and a communication control component to abandon the data that is subsequently received from such one computer by outputting the transmission permission signal in accordance with an output of the detecting component. When the abnormality occurs, the switch circuit releases such another computer, thereby disconnecting such one computer and such another computer. When reception commands prepared in the buffer area of such another computer are perfectly used, such another computer abandons the packet which does not include the flag to instruct the continuous reception.

摘要翻译： 一种其中多个计算机相互连接的计算机系统的数据通信系统包括：多个计算机，每个计算机具有存储基于该数据通信的命令的区域和用于存储数据的缓冲区; 开关电路，用于相互选择性地连接所述多个计算机; 以及连接在所述开关电路和所述多个计算机中的一个之间的传输允许部件，用于输出信号以允许从所述一台计算机向所述另一计算机的数据传输; 通信部件，用于通过从所述开关电路向所述另一计算机输出从所述传输许可部件发送所述传输许可信号，发送从所述一台计算机接收的数据; 检测部件，用于检测从所述一台计算机到所述另一计算机的关于所述数据通信的异常的发生; 以及通信控制部件，通过根据检测部件的输出输出发送许可信号，放弃随后从这样的计算机接收到的数据。 当异常发生时，开关电路释放这样的另一台计算机，从而断开这样一台计算机和另一台计算机。 当在这样的另一计算机的缓冲区中准备的接收命令被完美地使用时，这样的另一台计算机放弃不包括该标志的分组来指示连续的接收。

公开(公告)号：US5867541A

公开(公告)日：1999-02-02

申请号：US441613

申请日：1995-05-15

申请人： Akira Tanaka ,  Kenichi Ishibashi ,  Takehisa Hayashi ,  Akira Yamagiwa

发明人： Akira Tanaka ,  Kenichi Ishibashi ,  Takehisa Hayashi ,  Akira Yamagiwa

IPC分类号： G06F13/42 ,  H04L7/00 ,  H04L7/033

CPC分类号： H04L7/0337 ,  H04L7/0037 ,  H04L7/0008

摘要： Data is transmitted from any one of a plurality of transmitters in synchronism with a first clock. A receiver receives the data in synchronism with the first clock and a second clock having a predetermined phase relationship with the first clock. Control information is previously held in the receiver regarding data reception conditions associated with the plurality of transmitters to control reception conditions of the receiver on the basis of the control information.

摘要翻译： 数据从多个发射机中的任何一个与第一时钟同步发送。 接收机与第一时钟同步地接收数据，第二时钟与第一时钟具有预定的相位关系。 先前在接收机中保持与多个发射机有关的数据接收条件的控制信息，以根据控制信息来控制接收机的接收条件。

公开(公告)号：US07177970B2

公开(公告)日：2007-02-13

申请号：US10274881

申请日：2002-10-22

申请人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

发明人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

IPC分类号： G06F13/14 ,  G06F13/36

CPC分类号： G06F13/4027 ,  G06F13/36

摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

摘要翻译： 在数据处理系统中，连接到其系统总线的多个模块被分配有标识符。 当源模块发起对另一个模块的拆分读取访问时，源模块发送访问目标模块的地址和源模块的标识符。 当向源模块发送响应时，目的地模块向其返回响应数据和源模块的标识符。 从目标模块检查标识符，源模块确定作为对发起的访问的响应返回的响应数据。

公开(公告)号：US06341323B2

公开(公告)日：2002-01-22

申请号：US09777960

申请日：2001-02-07

申请人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

发明人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

IPC分类号： G06F1300

CPC分类号： G06F13/4027 ,  G06F13/36

摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

摘要翻译： 在数据处理系统中，连接到其系统总线的多个模块被分配有标识符。 当源模块发起对另一个模块的拆分读取访问时，源模块发送访问目标模块的地址和源模块的标识符。 当向源模块发送响应时，目的地模块向其返回响应数据和源模块的标识符。 从目标模块检查标识符，源模块确定作为对发起的访问的响应返回的响应数据。

公开(公告)号：US6005599A

公开(公告)日：1999-12-21

申请号：US363331

申请日：1994-12-23

申请人： Mitsuo Asai ,  Yoshihiro Takiyasu ,  Koichi Shibata ,  Mikiko Sato ,  Atsushi Saito ,  Takehisa Hayashi ,  Masaru Igawa

发明人： Mitsuo Asai ,  Yoshihiro Takiyasu ,  Koichi Shibata ,  Mikiko Sato ,  Atsushi Saito ,  Takehisa Hayashi ,  Masaru Igawa

IPC分类号： G06F13/00 ,  H04N5/765 ,  H04N5/781 ,  H04N5/783 ,  H04N5/85 ,  H04N5/926 ,  H04N5/93 ,  H04N7/10 ,  H04N7/173 ,  H04N21/231 ,  H04N21/2387

CPC分类号： H04N7/10 ,  H04N5/926 ,  H04N5/765 ,  H04N5/781 ,  H04N5/783 ,  H04N5/85

摘要： In a video storage and delivery apparatus and corresponding system, video data items are simultaneously supplied to a plurality of users while guaranteeing the time axis and the picture quality of the video data. The apparatus includes a frame address table which indicates a storage location in the apparatus of each frame of video data to start a special reproduction or a reproduction at a desired frame and a control unit controlling a switch bus connecting a plurality of video storage and delivery apparatuses to a plurality of channels so as to conduct data transfers via the switch bus between the apparatuses and between video reproduction devices of the users. From an optical disk data storage storing video data, a plurality of video data items are read in a timesharing fashion to be temporarily stored in a magnetic disk device or a semiconductor memory, thereby delivering the video data items therefrom to the users.

摘要翻译： 在视频存储和传送装置和相应的系统中，视频数据项同时提供给多个用户，同时保证视频数据的时间轴和图像质量。 该装置包括帧地址表，其指示在每个视频数据帧的装置中的存储位置，以开始特定再现或在期望帧的再现;以及控制单元，控制连接多个视频存储和传送装置的开关总线 到多个信道，以便经由设备之间的交换总线和用户的视频再现设备之间进行数据传送。 从存储视频数据的光盘数据存储器中，以分时方式读取多个视频数据项，临时存储在磁盘装置或半导体存储器中，由此向用户传送视频数据。