公开(公告)号：US06828607B1

公开(公告)日：2004-12-07

申请号：US10315458

申请日：2002-12-09

申请人： Mario M. Pelella ,  Amy C. Tu ,  Richard K. Klein

发明人： Mario M. Pelella ,  Amy C. Tu ,  Richard K. Klein

IPC分类号： H01L29768

CPC分类号： H01L21/76897 ,  H01L21/76831 ,  H01L23/485 ,  H01L27/115 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multiple independent bit Flash memory cell has a gate that includes a first oxide layer, a discontinuous nitride layer on the first oxide layer, a second oxide layer on the discontinuous nitride layer and the first oxide layer, and a polysilicon layer on the second oxide layer. The discontinuous nitride layer has regions residing at different portions of the layer. These portions are separated by the second oxide layer. Thus, with a smaller channel length, charge that otherwise would migrate from one region to the other and/or strongly influence its neighboring it is blocked/impeded by the second oxide layer. In this manner, the potential for charge sharing between the regions is reduced, and a higher density chip multiple independent bit Flash memory cells may be provided.

摘要翻译： 多独立位闪存单元具有栅极，该栅极包括第一氧化物层，第一氧化物层上的不连续氮化物层，不连续氮化物层上的第二氧化物层和第一氧化物层，以及在第二氧化物层上的多晶硅层 层。 不连续的氮化物层具有位于该层的不同部分的区域。 这些部分被第二氧化物层分离。 因此，具有较小的通道长度，否则会从一个区域迁移到另一个区域的电荷和/或强烈影响其邻近的电荷被第二氧化物层阻挡/阻碍。 以这种方式，减小了区域之间的电荷共享的可能性，并且可以提供更高密度的芯片多个独立的位闪存单元。

公开(公告)号：US07465639B1

公开(公告)日：2008-12-16

申请号：US11133969

申请日：2005-05-20

申请人： Mario M. Pelella ,  Richard K. Klein ,  James Werking

发明人： Mario M. Pelella ,  Richard K. Klein ,  James Werking

IPC分类号： H01L21/20

CPC分类号： H01L21/84

摘要： A method is provided for fabricating a silicon on insulator (SOI) device that includes a silicon substrate, a buried insulator layer overlying the silicon substrate, and a monocrystalline silicon layer overlying the buried insulator layer. The method comprises the steps of forming an MOS capacitor coupled between a first voltage bus and a second voltage bus. The MOS capacitor has a gate electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the gate electrode material forming a second plate of the MOS capacitor. The first voltage bus is coupled to the first plate of the capacitor and the second voltage bus is coupled to the second plate of the capacitor. The method further includes forming an electrical discharge path coupling the second plate of the MOS capacitor to the silicon substrate.

摘要翻译： 提供了一种用于制造绝缘体上硅（SOI）器件的方法，该器件包括硅衬底，覆盖硅衬底的掩埋绝缘体层和覆盖在掩埋绝缘体层上的单晶硅层。 该方法包括以下步骤：形成耦合在第一电压总线和第二电压总线之间的MOS电容器。 MOS电容器具有形成MOS电容器的第一板的栅电极材料和形成MOS电容器的第二板的栅极电极材料下面的单晶硅层中的杂质掺杂区域。 第一电压总线耦合到电容器的第一板，第二电压总线耦合到电容器的第二板。 该方法还包括形成将MOS电容器的第二板耦合到硅衬底的放电路径。

公开(公告)号：US07205825B2

公开(公告)日：2007-04-17

申请号：US10315393

申请日：2002-12-09

申请人： Richard K. Klein ,  Mario M. Pelella

发明人： Richard K. Klein ,  Mario M. Pelella

IPC分类号： G05F1/10

CPC分类号： H01L29/78615 ,  H03K19/0027 ,  H03K2005/00071 ,  H03K2217/0018

摘要： A method and apparatus for reducing the number of stages for measuring first and second switching speeds for PD/SOI transistors uses an inverter circuit which includes: a p-channel body-tied transistor; an n-channel body-tied transistor, coupled at their drains and gates; and a first and a second group of components tied to the bodies of the transistors. The first group restores body potentials for the transistors if the inverter circuit belongs to an even numbered stage of a ring oscillator. The second group provides body potentials for the transistors if the inverter circuit belongs to an odd numbered stage. After each transition of a waveform, the body potentials for the PD/SOI transistors are restored to the original potentials as stored in the capacitors. In this manner, a much smaller ring oscillator with fewer number of stages may be used to accurately measure the first and second switching speeds.

摘要翻译： 用于减少用于测量PD / SOI晶体管的第一和第二开关速度的级数的方法和装置使用的逆变器电路包括：p沟道体结晶体管; 在其下水道和门上耦合的n沟道体结晶体管; 以及连接到晶体管的主体的第一组和第二组元件。 如果逆变器电路属于环形振荡器的偶数级，则第一组恢复晶体管的体电位。 如果逆变器电路属于奇数级，则第二组提供晶体管的体电位。 在波形的每次转换之后，PD / SOI晶体管的体电位恢复到存储在电容器中的原始电位。 以这种方式，可以使用具有较少级数的更小的环形振荡器来精确地测量第一和第二切换速度。

公开(公告)号：US06046478A

公开(公告)日：2000-04-04

申请号：US937496

申请日：1997-09-25

申请人： Richard K. Klein

发明人： Richard K. Klein

IPC分类号： H01L21/8244 ,  H01L29/76

CPC分类号： H01L27/11

摘要： A device structure and a method of forming the structure comprising a thin film transistor (TFT) in a contact opening of a conventional field effect transistor (FET) by using .alpha.-silicon in the opening and the vertical portion of the .alpha.-silicon functioning as the channel for the TFT and both the FET and TFT sharing a common drain contact.

摘要翻译： 在常规场效应晶体管（FET）的接触开口中通过在开关中使用α-硅晶体形成该薄膜晶体管（TFT）的结构的装置结构和方法，其中所述α硅晶体的功能为 TFT的通道和FET和TFT共用共用漏极触点。

公开(公告)号：US5930659A

公开(公告)日：1999-07-27

申请号：US986098

申请日：1997-12-05

申请人： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

发明人： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

IPC分类号： H01L21/321 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/324

CPC分类号： H01L21/76888 ,  H01L21/32105 ,  H01L21/76838

摘要： A method of forming minimal gaps or spaces in a polysilicon conductive lines pattern for increasing the density of integrated circuits by converting an area of the size of the desired gap or space in the polysilicon to silicon oxide, followed by removing the silicon oxide. The preferred method is to selectively ion implant oxygen into the polysilicon and annealing to convert the oxygen implanted polysilicon to silicon oxide. As an alternative method, an opening in an insulating layer overlying the conductive line is first formed by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening and using the sidewalls as a mask to blanket implant oxygen through the reduced opening and into the exposed polysilicon conductive line. After annealing, the implanted polysilicon converted to silicon oxide and removed to form a gap or space in the polysilicon conductive line pattern substantially equal in size to the reduced opening. Instead of blanket implanting with oxygen, thermal oxidation can be used to convert the exposed polysilicon to silicon oxide.

摘要翻译： 通过将多晶硅中期望的间隙或空间的大小的面积转换为氧化硅，然后除去氧化硅，形成多晶硅导电线图形中的最小间隙或间隔的方法，以增加集成电路的密度。 优选的方法是选择性地将氧注入到多晶硅中并进行退火以将氧注入的多晶硅转化为氧化硅。 作为替代方法，首先通过常规光学光刻形成覆盖在导电线上的绝缘层中的开口，随后在开口中形成侧壁以形成减小的开口，并且使用侧壁作为掩模，以通过缩小开口来覆盖氧气注入氧气 并进入暴露的多晶硅导电线。 在退火之后，注入的多晶硅转变成氧化硅并去除，以在多晶硅导电线图案中形成与缩小的开口大致相等的间隙或空间。 代替用氧气进行全面注入，可以使用热氧化来将暴露的多晶硅转化为氧化硅。

公开(公告)号：US06297083B1

公开(公告)日：2001-10-02

申请号：US09263394

申请日：1999-03-05

申请人： Richard K. Klein

发明人： Richard K. Klein

IPC分类号： H01L218244

CPC分类号： H01L27/11 ,  H01L27/1112

摘要： A device structure and a method of forming the structure comprising a resistor in a via opening between adjacent levels of metallization of a conventional field effect transistor (FET) by using amphorous (&agr;) silicon between metal barrier layers, such as titanium tungsten and titanium nitride, at the via opening which is filled with a conductive material, such as tungsten said device structure and method enabling a conventional FET and resistor to only take the space of a conventional FET due to the unique properties of &agr;-silicon.

摘要翻译： 一种器件结构和方法，其通过在金属阻挡层（例如钛钨和氮化钛）之间使用两相（α）硅，在常规场效应晶体管（FET）的相邻金属化层之间的通孔开口中形成电阻器 在填充有导电材料（例如钨）的通孔开口处，所述器件结构和方法使常规FET和电阻器仅由于α硅的独特性能而仅占用常规FET的空间。

公开(公告)号：US5907175A

公开(公告)日：1999-05-25

申请号：US937676

申请日：1997-09-25

申请人： Richard K. Klein

发明人： Richard K. Klein

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L29/76 ,  H01L27/01 ,  H01L29/00

CPC分类号： H01L27/11 ,  H01L27/1112

摘要： A device structure comprising a resistor in a via opening between adjacent levels of metallization of a conventional field effect transistor (FET) by disposing amorphous (.alpha.) silicon between metal barrier layers, such as titanium tungsten and titanium nitride, at the via opening which is filled with a conductive material, such as tungsten, the device structure enabling a conventional FET and the resistor to only take the space of a conventional FET due to the unique properties of .alpha.-silicon.

摘要翻译： 一种器件结构，其包括通过在常规场效应晶体管（FET）的相邻金属化层之间的通孔中的电阻器，通过在诸如钛钨和氮化钛的金属阻挡层（例如钛钨和氮化钛）之间设置无定形（α）硅， 填充有诸如钨的导电材料，由于α硅的独特性质，器件结构使常规FET和电阻器仅占用常规FET的空间。

公开(公告)号：US4960732A

公开(公告)日：1990-10-02

申请号：US436399

申请日：1989-11-14

申请人： Pankaj Dixit ,  Jack Sliwa ,  Richard K. Klein ,  Craig S. Sander ,  Mohammad Farnaam

发明人： Pankaj Dixit ,  Jack Sliwa ,  Richard K. Klein ,  Craig S. Sander ,  Mohammad Farnaam

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/76877 ,  H01L21/76879

摘要： A stable, low resistance contact is formed in a contact hole (16) through an insulating layer (14), e.g., silicon dioxide, formed on a surface of a semiconductor substrate (12), e.g., silicon, to a portion of a doped region (10) in said semiconductor surface. The contact comprises (a) an adhesion and contacting layer (18) of titanium formed along the walls of the insulating layer and in contact with the portion of the doped region; (b) a barrier layer (20) formed over the adhesion and contacting layer; and (c) a conductive material (22) formed over the barrier layer and at least substantially filling said contact hole. A patterned metal layer (26) forms an ohmic contact interconnect to other devices and external circuitry.The adhesion and contacting layer and barrier layer are either physically or chemically vapor deposited onto the oxide surface. The conductive layer comprises one of CVD or bias sputtered tungsten, molybdenum or in situ doped CVD polysilicon.The contact of the invention avoids the problems of encroachment at the oxide-silicon interface and worm holes associated with other contact schemes but retains process simplicity.

摘要翻译： 在通过绝缘层（14）的接触孔（16）中形成稳定的低电阻接触，所述绝缘层（例如，二氧化硅）形成在半导体衬底（12）（例如硅）的表面上， 区域（10）。 触点包括（a）沿着绝缘层的壁形成并与掺杂区域的部分接触的钛的粘合和接触层（18）; （b）形成在粘附和接触层上的阻挡层（20）; 和（c）导电材料（22），其形成在所述阻挡层上并且至少基本上填充所述接触孔。 图案化金属层（26）与其它器件和外部电路形成欧姆接触互连。 粘附和接触层和阻挡层物理或化学气相沉积到氧化物表面上。 导电层包括CVD或偏置溅射的钨，钼或原位掺杂的CVD多晶硅中的一种。 本发明的接触避免了在与其它接触方案相关联的氧化物 - 硅界面和蠕虫孔上侵占的问题，但是保持了工艺简单性。

公开(公告)号：US4951112A

公开(公告)日：1990-08-21

申请号：US280782

申请日：1988-12-07

申请人： Tat C. Choi ,  Richard K. Klein ,  Craig S. Sander

发明人： Tat C. Choi ,  Richard K. Klein ,  Craig S. Sander

IPC分类号： G11C11/412 ,  H01L21/8244 ,  H01L27/11

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L27/1112 ,  Y10S257/904

摘要： A 4T static RAM cell (10) comprising a flip-flop with two pull-down transistors (18, 20) and two pass-gate transistors (12, 14) is fabaricated employing two separate gate oxide formations (74, 76) and associated separate polysilicon depositions (52a -b, 56). Two reduced area contacts (58, 60) connect to the nodes (26, 30) of the circuit (10). The reduced area butting contacts comprise vertically-disposed, doped polysilicon plugs (94), which intersect and electrically interconnect buried polysilicon layers (load poly 88, gate poly 52a) with doped silicon regions (80) in a bottom layer. Adding the processing steps of forming separate gate oxides for the pull-down and pass-gate transistors results in a smaller cell area and reduces the requirements of the contacts from three to two. Further, the separate gate oxidations permit independent optimization of the pull-down and pass-gate transistors.

摘要翻译： 包括具有两个下拉晶体管（18,20）和两个通过栅晶体管（12,14）的触发器的4T静态RAM单元（10）通过采用两个单独的栅极氧化物层（74,76）和相关联的 分离的多晶硅沉积物（52a-b，56）。 两个缩小区域触点（58,60）连接到电路（10）的节点（26,30）。 减小面积对接触点包括垂直布置的掺杂多晶硅插塞（94），其在底层中与埋入的多晶硅层（负载聚合物88，栅极聚合物52a）和掺杂的硅区域（80）电互连。 为下拉和栅极晶体管添加形成单独的栅极氧化物的处理步骤导致更小的单元面积，并将触点的要求从三个减少到两个。 此外，单独的栅极氧化允许下拉和栅极晶体管的独立优化。

公开(公告)号：US06191034B1

公开(公告)日：2001-02-20

申请号：US09286401

申请日：1999-04-05

申请人： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

发明人： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

IPC分类号： H01L2144

CPC分类号： H01L21/76892 ,  H01L21/32139

摘要： A method of forming minimal gaps or spaces in conductive lines pattern for increasing the density of integrated circuits by first forming an opening in an insulating layer overlying the conductive line by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening, and using the sidewalls as a mask to remove, preferably by etching, a portion of the conductive line pattern substantially equal in size to the reduced opening.

摘要翻译： 在导电线图案中形成最小间隙或空间的方法，用于通过首先在通过常规光学平版印刷在导电线上的绝缘层中形成开口，随后在开口中形成减小开口的侧壁，从而增加集成电路的密度， 并且使用所述侧壁作为掩模，优选地通过蚀刻除去所述导电线图案的大小与所述减小的开口大致相等的部分。