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1.发明授权Method of making a multi-bit non-volatile memory (NVM) cell and structure 有权制造多位非易失性存储器（NVM）单元和结构的方法公开(公告)号：US07364970B2
公开(公告)日：2008-04-29
申请号：US11240242
申请日：2005-09-30
IPC分类号： H01L21/8247
CPC分类号： H01L21/28273 , H01L29/42332
摘要： A multi-bit non volatile memory cell includes a first floating gate sidewall spacer structure and a second floating gate sidewall spacer structure physically separated from the first floating gate sidewall spacer structure. Each floating gate sidewall spacer structure stores charge for logically storing a bit. The floating gate sidewall spacer structures are formed adjacent to a patterned structure by sidewall spacer formation processes from a layer of floating gate material (e.g. polysilicon). A control gate is formed over the floating gate sidewall spacer structures by forming a layer of control gate material and then patterning the layer of control gate material.
摘要翻译： 多位非易失性存储单元包括第一浮栅侧壁间隔结构和与第一浮栅侧壁间隔结构物理分离的第二浮栅侧壁间隔结构。 每个浮栅侧壁间隔结构存储逻辑存储位的电荷。 通过从浮置栅极材料层（例如多晶硅）的侧壁间隔物形成工艺，将浮栅侧壁间隔结构形成为与图案化结构相邻。 通过形成控制栅极材料层，然后对控制栅极材料层进行图案化，在浮栅侧壁间隔结构上形成控制栅极。
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公开(公告)号：US07312129B2
公开(公告)日：2007-12-25
申请号：US11339101
申请日：2006-01-25
IPC分类号： H01L21/336
CPC分类号： H01L21/28132 , H01L21/823437 , H01L21/823468 , H01L27/0705 , H01L29/66484 , H01L29/7831
摘要： A semiconductor process and apparatus use a predetermined sequence of patterning and etching steps to etch a gate stack (62) formed over a substrate (11) and a first spacer structure (42), thereby forming etched gate structures (72, 74) that are physically separated from one another but that control a substrate channel (71) subsequently defined in the substrate (11) by source/drain regions (82, 102, 84, 104) that are implanted around the etched gate structures (72, 74). Depending on how the first spacer structure (42) is positioned and configured, the channel (71) may be controlled to provide either a logical AND gate (100) or logical OR gate (200) functionality.
摘要翻译： 半导体工艺和装置使用预定的图案化和蚀刻步骤序列来蚀刻在衬底（11）和第一间隔结构（42）上形成的栅极堆叠（62），从而形成蚀刻的栅极结构（72,74），其是 在物理上彼此分离，但是通过植入在蚀刻的栅极结构（72,74）周围的源极/漏极区域（82,102,84,104）来控制随后在衬底（11）中限定的衬底沟道（71）。 取决于第一间隔结构（42）如何定位和配置，通道（71）可被控制以提供逻辑与门（100）或逻辑或门（200）功能。
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公开(公告)号：US07235847B2
公开(公告)日：2007-06-26
申请号：US10944306
申请日：2004-09-17
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/42372
摘要： A semiconductor device (10) having a gate (16, 18 or 16, 18, 26, 28) with a thin conductive layer (18) is described. As the physical dimensions of semiconductor devices are scaled below the sub-micron regime, very thin gate dielectrics (16) are used. One problem encountered with very thin gate dielectrics is that the carriers can tunnel through the gate dielectric material, thus increasing the undesirable leakage current in the device. By using a thin layer for conductive layer (18), quantum confinement of carriers within conductive layer (18) can be induced. This quantum confinement removes modes which are propagating in the direction normal to the interfacial plane 15 from the Fermi level. Thus, the undesirable leakage current in the device (10) can be reduced. Additional conductive layers (e.g. 28) may be used to provide more carriers.
摘要翻译： 描述了具有薄导电层（18）的栅极（16,18或16,18,26,28）的半导体器件（10）。 由于半导体器件的物理尺寸缩小到亚微米级以下，所以使用非常薄的栅极电介质（16）。 非常薄的栅极电介质遇到的一个问题是载流子可以穿过栅极电介质材料，从而增加器件中不希望的泄漏电流。 通过使用用于导电层（18）的薄层，可以诱导导电层（18）内的载流子的量子限制。 该量子限制去除了从费米能级垂直于界面15的方向传播的模式。 因此，可以减少装置（10）中不期望的泄漏电流。 附加的导电层（例如28）可用于提供更多的载体。
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公开(公告)号：US08314448B2
公开(公告)日：2012-11-20
申请号：US13105484
申请日：2011-05-11
IPC分类号： H01L29/80
CPC分类号： H01L29/66795 , H01L29/41791 , H01L29/785 , H01L2029/7858
摘要： Embodiments of a semiconductor structure include a first current electrode region, a second current electrode region, and a channel region. The channel region is located between the first current electrode region and the second current electrode region, and the channel region is located in a fin structure of the semiconductor structure. A carrier transport in the channel region is generally in a horizontal direction between the first current electrode region and the second current electrode region.
摘要翻译： 半导体结构的实施例包括第一电流电极区域，第二电流电极区域和沟道区域。 沟道区域位于第一电流电极区域和第二电流电极区域之间，沟道区域位于半导体结构的鳍结构中。 通道区域中的载流子传输通常在第一电流电极区域和第二电流电极区域之间的水平方向上。
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公开(公告)号：US07927956B2
公开(公告)日：2011-04-19
申请号：US11609664
申请日：2006-12-12
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/1054 , H01L21/02126 , H01L21/02164 , H01L21/02236 , H01L21/31658 , H01L21/32105 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , Y10S438/933
摘要： A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying the silicon layer. Alternatively, germanium is implanted into a top portion of the silicon layer to form an amorphous silicon germanium layer. The silicon germanium layer is then oxidized to convert the silicon germanium layer into a silicon dioxide layer and to convert at least a portion of the silicon layer into germanium-rich silicon. The silicon dioxide layer is then removed prior to forming transistors using the germanium-rich silicon. In one embodiment, the germanium-rich silicon is selectively formed using a patterned masking layer over the silicon layer and under the silicon germanium layer. Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.
摘要翻译： 提供了具有硅层的半导体衬底。 在一个实施例中，衬底是具有在硅层下面的氧化物层的绝缘体上硅（SOI）衬底。 在硅层上形成非晶或多晶硅锗层。 或者，将锗注入硅层的顶部以形成非晶硅锗层。 然后氧化硅锗层以将硅锗层转化为二氧化硅层，并将至少一部分硅层转化为富含锗的硅。 然后在使用富含锗的硅形成晶体管之前去除二氧化硅层。 在一个实施例中，使用硅层上方的图案化掩模层和硅锗层选择性地形成富锗富硅。 或者，可以使用隔离区来限定其中形成富锗的硅的衬底的局部区域。
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6.发明授权Electronic device including a fin-type transistor structure and a process for forming the electronic device 有权包括鳍型晶体管结构的电子器件和用于形成电子器件的工艺公开(公告)号：US07723805B2
公开(公告)日：2010-05-25
申请号：US11328594
申请日：2006-01-10
IPC分类号： H01L27/088
CPC分类号： H01L29/785 , H01L21/823431 , H01L29/66795
摘要： An electronic device can include an insulating layer and a fin-type transistor structure. The fin-type structure can have a semiconductor fin and a gate electrode spaced apart from each other. A dielectric layer and a spacer structure can lie between the semiconductor fin and the gate electrode. The semiconductor fin can include channel region including a portion associated with a relatively higher VT lying between a portion associated with a relatively lower VT and the insulating layer. In one embodiment, the supply voltage is lower than the relatively higher VT of the channel region. A process for forming the electronic device is also disclosed.
摘要翻译： 电子器件可以包括绝缘层和鳍型晶体管结构。 翅片型结构可以具有彼此间隔开的半导体翅片和栅电极。 电介质层和间隔结构可以位于半导体鳍片和栅电极之间。 半导体鳍片可以包括沟道区域，其包括与位于与相对较低的VT相关联的部分和绝缘层之间的相对较高的VT相关联的部分。 在一个实施例中，电源电压低于通道区域的相对较高的VT。 还公开了一种用于形成电子器件的工艺。
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公开(公告)号：US20090115001A1
公开(公告)日：2009-05-07
申请号：US12347061
申请日：2008-12-31
IPC分类号： H01L29/78
CPC分类号： H01L29/4975 , H01L21/28097 , H01L29/517 , H01L29/518 , H01L29/78
摘要： An embodiment of a semiconductor device includes a semiconductor substrate having a principal surface, spaced-apart source and drain regions separated by a channel region at the principal surface, and a multilayered gate structure located over the channel region. The multilayered gate structure includes a gate dielectric layer in contact with the channel region, a first conductor comprising a metal oxide overlying the gate dielectric layer, a second conductor overlying the first conductor, and an impurity migration inhibiting layer between the gate dielectric layer and the first conductor or between the first conductor and the second conductor.
摘要翻译： 半导体器件的实施例包括半导体衬底，其具有主表面，间隔开的源极和漏极区域，其在主表面处由沟道区域分隔开，并且多层栅极结构位于沟道区域上方。 多层栅极结构包括与沟道区接触的栅极电介质层，包括覆盖栅极电介质层的金属氧化物的第一导体，覆盖第一导体的第二导体以及在栅极介电层和第二导体之间的杂质迁移抑制层 第一导体或第一导体与第二导体之间。
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公开(公告)号：US20070281446A1
公开(公告)日：2007-12-06
申请号：US11443627
申请日：2006-05-31
IPC分类号： H01L21/20
CPC分类号： H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/785
摘要： A semiconductor process and apparatus provide a planarized hybrid substrate (18) by exposing a buried oxide layer (80) in a first area (99), selectively etching the buried oxide layer (80) to expose a first semiconductor layer (70) in a second smaller seed area (98), and then epitaxially growing a first epitaxial semiconductor material from the seed area (98) of the first semiconductor layer (70) that fills the second trench opening (100) and grows laterally over the exposed insulator layer (80) to fill at least part of the first trench opening (99), thereby forming a first epitaxial semiconductor layer (101) that is electrically isolated from the second semiconductor layer (90). By forming a first SOI transistor device (160) over a first SOI layer (90) using deposited (100) silicon and forming first SOI transistor (161) over an epitaxially grown (110) silicon layer (101), a high performance CMOS device is obtained.
摘要翻译： 半导体工艺和装置通过在第一区域（99）中暴露掩埋氧化物层（80）来提供平坦化的混合衬底（18），选择性地蚀刻掩埋氧化物层（80）以暴露第一半导体层 第二较小种子区域（98），然后从填充第二沟槽开口（100）的第一半导体层（70）的种子区域（98）外延生长第一外延半导体材料，并在暴露的绝缘体层上横向生长 80）以填充第一沟槽开口（99）的至少一部分，从而形成与第二半导体层（90）电隔离的第一外延半导体层（101）。 通过使用沉积的（100）硅并在外延生长（110）硅层（101）上形成第一SOI晶体管（161）在第一SOI层（90）上形成第一SOI晶体管器件（160），高性能CMOS器件 获得。
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公开(公告)号：US5985736A
公开(公告)日：1999-11-16
申请号：US949825
申请日：1997-10-14
申请人： Marius K. Orlowski , Karl Wimmer
发明人： Marius K. Orlowski , Karl Wimmer
IPC分类号： H01L21/32 , H01L21/762
CPC分类号： H01L21/76202 , H01L21/32
摘要： Field isolation regions are formed using oxidation-resistant spacers or plugs that completely fill trenches within a semiconductor substrate prior to forming the field isolation regions. The spacers or plugs help to reduce encroachment of the field isolation regions under the spacers or plugs. The structure used as an oxidation mask for the field isolation process may include a silicon-containing member that is thicker than an overlying oxidation-resistant member. The thicker silicon-containing member may be capable of tolerating higher stress before defects in an underlying pad layer or substrate are formed.
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10.发明授权
公开(公告)号：US5705415A
公开(公告)日：1998-01-06
申请号：US324423
申请日：1994-10-04
申请人： Marius K. Orlowski , Ko-Min Chang
发明人： Marius K. Orlowski , Ko-Min Chang
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11556 , H01L27/115
摘要： A semiconductor device is formed having a floating gate memory cell (11) that has its channel region (33) oriented vertically with a portion of the channel region (33) that is not capacitively coupled to a floating gate (32). The memory cell (11) is less likely to be over-erased and may be programmed by source-side injection. The cell (11) may not need to be repaired after erasing. Less power may be consumed during programming compared to hot electron injection and Fowler-Nordheim tunneling.
摘要翻译： 形成具有浮动栅极存储单元（11）的半导体器件，其浮动栅极存储单元（11）的沟道区域（33）垂直定向，而沟道区域（33）的一部分不与浮动栅极电容耦合。 存储单元（11）不太可能被过度擦除，并且可以通过源侧注入来编程。 擦除后，电池（11）可能不需要修理。 与热电子注入和Fowler-Nordheim隧道相比，编程期间可能消耗较少的功率。
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