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1.发明授权Method for achieving a high quality thin oxide in integrated circuit devices 失效在集成电路器件中实现高品质薄氧化物的方法
公开(公告)号：US5362685A
公开(公告)日：1994-11-08
申请号：US969708
申请日：1992-10-29
IPC分类号： H01L21/28 , H01L21/316 , H01L21/762 , H01L21/8247 , H01L29/788 , H01L29/792 , H01L21/266
CPC分类号： H01L27/11517 , H01L21/02238 , H01L21/02255 , H01L21/28273 , H01L21/31662 , H01L21/76202 , Y10S438/981
摘要： The quality of both a gate oxide and a tunnel oxide in a P-well active area of a CMOS EEPROM process is improved by reducing the field edge pullback arising from wet chemical etch steps prior to the growth of the gate and tunnel oxides. A first oxide is grown, and an implant is performed through the first oxide to form an implanted layer. The surface of the first oxide is then cleaned without removing all of the first oxide overlying the implanted layer. An anneal step then activates the implanted layer to form a heavily-doped region, after which the remaining first oxide is then removed. A second oxide is then grown, and a region of the second oxide is removed overlying the heavily-doped region. Lastly, a tunnel oxide is grown over the heavily-doped region while re-oxidizing the second oxide to form a gate oxide thicker than the tunnel oxide.
摘要翻译： 在CMOS EEPROM工艺的P阱有源区域中的栅极氧化物和隧道氧化物的质量通过减少在栅极和隧道氧化物生长之前由湿化学蚀刻步骤引起的场边缘回退而得到改善。 生长第一氧化物，并且通过第一氧化物进行注入以形成注入层。 然后清洁第一氧化物的表面，而不去除覆盖在注入层上的所有第一氧化物。 退火步骤然后激活注入层以形成重掺杂区域，此后剩余的第一氧化物被除去。 然后生长第二氧化物，并且去除重掺杂区域上的第二氧化物的区域。 最后，在重掺杂区域上生长隧道氧化物，同时再次氧化第二氧化物以形成比隧道氧化物更厚的栅极氧化物。
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2.发明授权
公开(公告)号：US5296411A
公开(公告)日：1994-03-22
申请号：US54324
申请日：1993-04-28
IPC分类号： H01L21/28 , H01L21/3105 , H01L21/3115 , H01L21/314 , H01L21/316 , H01L29/51 , H01L21/02
CPC分类号： H01L21/28185 , H01L21/02238 , H01L21/02255 , H01L21/02337 , H01L21/3105 , H01L21/3115 , H01L21/3144 , H01L21/31662 , H01L29/518 , H01L21/28167 , H01L21/28202 , H01L21/28211
摘要： A high-quality tunnel oxide, suitable for EEPROM devices, is formed upon a surface region of a semiconductor body over a heavily-doped N+ layer by first oxidizing the semiconductor body to form an oxide upon the surface region of the semiconductor body over the heavily-doped N+ layer. Next, the semiconductor body is annealed, under a gettering ambient, to densify the oxide and to dope the oxide at its surface and for a portion thereinto near its surface with a gettering agent. The semiconductor body is then oxidized, under an oxidizing ambient, to thicken the oxide, after which it is annealed for a second time, this time under an oxidizing ambient containing nitrogen, to further thicken the oxide and to form a surface layer therein containing a concentration of nitrogen. Tunnel oxides thus fabricated exhibit dramatically improved time-to-breakdown characteristics compared to tunnel oxides processed without such a nitrogen anneal. Furthermore, gate oxides formed earlier in a process sequence, but receiving the same nitrogen anneal, also exhibit markedly improved time-to-breakdown characteristics, as well as substantially improved threshold stability in response to a fixed current passed through the gate oxide.
摘要翻译： 通过首先氧化半导体体以在半导体主体的表面区域上形成氧化物，在重掺杂的N +层上的半导体本体的表面区域上形成适用于EEPROM器件的高品质隧道氧化物， 掺杂的N +层。 接下来，在吸气环境下，将半导体本体退火以使氧化物致密化并在其表面上掺杂氧化物，并在其表面附近用吸杂剂掺杂一部分。 然后在氧化环境下氧化半导体体，使氧化物变厚，然后将其退火第二次，此时在含有氮的氧化环境下进一步增厚氧化物，并形成其中含有 氮浓度 与没有进行氮退火处理的隧道氧化物相比，如此制造的隧道氧化物显示出显着改善的时间到击穿特性。 此外，在工艺顺序中较早形成但接受相同氮退火的栅极氧化物也显示出显着改善的击穿时间特性，以及响应于通过栅极氧化物的固定电流而显着改善阈值稳定性。
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3.发明授权Oxide removal method for improvement of subsequently grown oxides for a twin-tub CMOS process 失效用于改进用于双盆CMOS工艺的随后生长的氧化物的氧化物去除方法
公开(公告)号：US5350491A
公开(公告)日：1994-09-27
申请号：US947313
申请日：1992-09-18
IPC分类号： H01L21/306 , H01L21/311 , H01L21/762 , H01L21/00 , B44C1/22 , C03C15/00 , H01L21/02
CPC分类号： H01L21/31111 , H01L21/76202
摘要： A method is disclosed for removing oxide from the surface of a semiconductor body having a thick oxide and an adjoining thin oxide, without subjecting the surface to significant over-etching and thus avoiding degradation of the surface of the semiconductor body. A photoresist layer is first deposited covering the thin oxide. The thick oxide is then etched for a period of time so that a portion of the thick oxide remains, and has a thickness comparable to that of the thin oxide. The photoresist layer covering the thin oxide is next removed without appreciably etching either the remaining portion of the thick oxide or the thin oxide. Finally, the thin oxide and the remaining portion of the thick oxide are removed, without appreciably over-etching the surface of the semiconductor body.
摘要翻译： 公开了一种从具有厚氧化物和邻接的薄氧化物的半导体主体的表面去除氧化物的方法，而不会使表面受到显着的过度蚀刻，从而避免了半导体本体的表面的劣化。 首先沉积覆盖薄氧化物的光致抗蚀剂层。 然后将厚氧化物蚀刻一段时间，使得一部分厚氧化物保留，并具有与薄氧化物相当的厚度。 接着去除覆盖薄氧化物的光致抗蚀剂层，而不会明显地蚀刻厚氧化物或薄氧化物的剩余部分。 最后，去除薄氧化物和厚氧化物的剩余部分，而不会明显地过度蚀刻半导体本体的表面。
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4.发明授权Method for achieving a high quality thin oxide using a sacrificial oxide anneal 失效使用牺牲氧化物退火获得高质量薄氧化物的方法
公开(公告)号：US5538923A
公开(公告)日：1996-07-23
申请号：US251070
申请日：1994-05-27
IPC分类号： H01L21/28 , H01L21/316 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/51 , H01L29/788 , H01L29/792 , H01L21/02
CPC分类号： H01L21/28185 , H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/31662 , H01L29/518 , H01L29/66825 , H01L21/28167 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L27/115 , Y10S438/981
摘要： The quality of both a gate oxide and a tunnel oxide in a P-well of a CMOS EEPROM process is improved by growing and subsequently annealing in-situ a gate oxide. A photoresist layer is then applied and defined to expose regions of the gate oxide which are then etched to expose the surface of the semiconductor, and after which the photoresist layer is removed. Subsequently, the remaining gate oxide is partially etched to reduce the thickness of the gate oxide and to remove any native oxide which may have formed over the exposed semiconductor surface. Finally, a tunnel oxide is grown upon the exposed semiconductor surface. The quality of this tunnel oxide is dramatically improved due to the in-situ anneal of the gate oxide, even though the gate oxide (in the region of the tunnel oxide) is totally removed before tunnel oxide growth. Furthermore, the re-oxidized gate oxide which was not entirely removed before tunnel oxide growth also exhibits higher breakdown voltages.
摘要翻译： CMOS EEPROM工艺的P阱中的栅极氧化物和隧道氧化物的质量通过生长并随后原位退火栅极氧化物得到改善。 然后施加和定义光致抗蚀剂层以暴露栅极氧化物的区域，然后蚀刻该栅极氧化物以露出半导体的表面，之后除去光致抗蚀剂层。 随后，剩余的栅极氧化物被部分蚀刻以减小栅极氧化物的厚度并去除可能在暴露的半导体表面上形成的任何天然氧化物。 最后，在暴露的半导体表面上生长隧道氧化物。 即使栅极氧化物（在隧道氧化物的区域中）在隧道氧化物生长之前被完全去除，由于栅极氧化物的原位退火，隧道氧化物的质量显着提高。 此外，在隧道氧化物生长之前未完全除去的再氧化的栅极氧化物也表现出更高的击穿电压。
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公开(公告)号：US5350492A
公开(公告)日：1994-09-27
申请号：US947314
申请日：1992-09-18
IPC分类号： H01L21/306 , H01L21/311 , H01L21/762 , H01L21/00 , B44C1/22 , C03C15/00 , H01L21/02
CPC分类号： H01L21/76202 , H01L21/31111 , Y10S438/911
摘要： A method is disclosed for removing oxide from the surface of a semiconductor body having a thick oxide and an adjoining nitride-covered thin oxide, without subjecting the surface to significant over-etching and thus avoiding degredation of the surface of the semiconductor body. The thick oxide is first etched for a period of time so that a portion of the thick oxide remains, and has a thickness comparable to that of the thin oxide. The nitride covering the thin oxide is next removed without appreciably etching either the remaining portion of the thick oxide or the thin oxide. Finally, the thin oxide and the remaining portion of the thick oxide are removed, without appreciably over-etching the surface of the semiconductor body.
摘要翻译： 公开了一种用于从具有厚氧化物和邻接的氮化物覆盖的薄氧化物的半导体主体的表面去除氧化物的方法，而不会使表面受到显着的过度蚀刻，从而避免半导体本体的表面变色。 首先蚀刻厚氧化物一段时间，使得一部分厚氧化物保留，并具有与薄氧化物相当的厚度。 覆盖薄氧化物的氮化物接下来被去除，而不明显地蚀刻厚氧化物或薄氧化物的剩余部分。 最后，去除薄氧化物和厚氧化物的剩余部分，而不会明显地过度蚀刻半导体本体的表面。
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6.发明授权Method for achieving a high quality thin oxide using a sacrificial oxide anneal 失效使用牺牲氧化物退火获得高质量薄氧化物的方法
公开(公告)号：US5316981A
公开(公告)日：1994-05-31
申请号：US959230
申请日：1992-10-09
IPC分类号： H01L21/28 , H01L21/316 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/51 , H01L29/788 , H01L29/792 , H01L21/02
CPC分类号： H01L21/28185 , H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/31662 , H01L29/518 , H01L29/66825 , H01L21/28167 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L27/115 , Y10S438/981
摘要： The quality of both a gate oxide and a tunnel oxide in a P-well of a CMOS EEPROM process is improved by growing and subsequently annealing in-situ a gate oxide. A photoresist layer is then applied and defined to expose regions of the gate oxide which are then etched to expose the surface of the semiconductor, and after which the photoresist layer is removed. Subsequently, the remaining gate oxide is partially etched to reduce the thickness of the gate oxide and to remove any native oxide which may have formed over the exposed semiconductor surface. Finally, a tunnel oxide is grown upon the exposed semiconductor surface. The quality of this tunnel oxide is dramatically improved due to the in-situ anneal of the gate oxide, even though the gate oxide (in the region of the tunnel oxide) is totally removed before tunnel oxide growth. Furthermore, the re-oxidized gate oxide which was not entirely removed before tunnel oxide growth also exhibits higher breakdown voltages.
摘要翻译： CMOS EEPROM工艺的P阱中的栅极氧化物和隧道氧化物的质量通过生长并随后原位退火栅极氧化物得到改善。 然后施加和定义光致抗蚀剂层以暴露栅极氧化物的区域，然后蚀刻该栅极氧化物以露出半导体的表面，之后除去光致抗蚀剂层。 随后，剩余的栅极氧化物被部分蚀刻以减小栅极氧化物的厚度并去除可能在暴露的半导体表面上形成的任何天然氧化物。 最后，在暴露的半导体表面上生长隧道氧化物。 即使栅极氧化物（在隧道氧化物的区域中）在隧道氧化物生长之前被完全去除，由于栅极氧化物的原位退火，隧道氧化物的质量显着提高。 此外，在隧道氧化物生长之前未完全除去的再氧化的栅极氧化物也表现出更高的击穿电压。
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7.发明授权公开(公告)号：US06979878B1
公开(公告)日：2005-12-27
申请号：US09217213
申请日：1998-12-21
IPC分类号： H01L21/762 , H01L29/36
CPC分类号： H01L21/76237
摘要： A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of dielectric spacers are formed upon the sidewalls of the masking layer within the opening. A trench is then etched in the semiconductor substrate between the dielectric spacers. A first dielectric layer is then thermally grown on the walls and base of the trench. A CVD oxide is deposited into the trench and processed such that the upper surface of the CVD oxide is commensurate with the substrate surface. Portions of the spacers are also removed such that the thickness of the spacers is between about 0 to 200 Å. Silicon atoms and/or barrier atoms, such as nitrogen atoms, are then implanted ino regions of the active areas in close proximity to the trench isolation structure.
摘要翻译： 一种用于将第一有源区与第二有源区隔离的方法，二者均配置在半导体衬底内。 该方法包括在半导体衬底上形成电介质掩模层。 然后通过掩模层形成开口。 在开口内的掩模层的侧壁上形成一对电介质隔离物。 然后在电介质间隔物之间的半导体衬底中蚀刻沟槽。 然后在沟槽的壁和基底上热生长第一介电层。 将CVD氧化物沉积到沟槽中并进行处理，使得CVD氧化物的上表面与衬底表面相当。 间隔物的一部分也被去除，使得间隔物的厚度在约0至200埃之间。 然后将硅原子和/或势垒原子（例如氮原子）注入非常靠近沟槽隔离结构的有源区的多个区域中。
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公开(公告)号：US06743688B1
公开(公告)日：2004-06-01
申请号：US09002964
申请日：1998-01-05
IPC分类号： H01L21336
CPC分类号： H01L21/28185 , H01L21/265 , H01L21/28202 , H01L21/28211 , H01L29/42368 , H01L29/518 , H01L29/66553 , H01L29/66583 , H01L29/78 , Y10S438/981
摘要： A semiconductor device having gate oxide with a first thickness and a second thickness is formed by initially implanting a portion of the gate area of the semiconductor substrate with nitrogen ions and then forming a gate oxide on the gate area. Preferably the gate oxide is grown by exposing the gate area to an environment of oxygen. A nitrogen implant inhibits the rate of SiO2 growth in an oxygen environment. Therefore, the portion of the gate area with implanted nitrogen atoms will grow or form a layer of gate oxide, such as SiO2, which is thinner than the portion of the gate area less heavily implanted or not implanted with nitrogen atoms. The gate oxide layer could be deposited rather than growing the gate oxide layer. After forming the gate oxide layer, polysilicon is deposited onto the gate oxide. The semiconductor substrate can then be implanted to form doped drain and source regions. Spacers can then be placed over the drain and source regions and adjacent the ends of the sidewalls of the gate.
摘要翻译： 具有第一厚度和第二厚度的栅极氧化物的半导体器件通过首先用氮离子注入半导体衬底的栅极区域的一部分，然后在栅极区域上形成栅极氧化物来形成。 优选地，通过将栅极区域暴露于氧气环境来生长栅极氧化物。 氮注入抑制氧气环境中的二氧化硅生长速率。 因此，具有植入氮原子的栅极区域的部分将生长或形成诸如SiO 2的栅极氧化物层，其比栅极区域较少注入或未注入氮原子的部分更薄。 可以沉积栅极氧化物层而不是生长栅极氧化物层。 在形成栅极氧化物层之后，将多晶硅沉积到栅极氧化物上。 然后可以注入半导体衬底以形成掺杂的漏极和源极区域。 然后可以将间隔物放置在漏极和源极区域上并且邻近栅极的侧壁的端部。
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9.发明授权Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant 失效具有由横向扩散的氮植入物限定的超短沟道长度的晶体管公开(公告)号：US06451657B1
公开(公告)日：2002-09-17
申请号：US09781044
申请日：2001-02-08
IPC分类号： H01L21336
CPC分类号： H01L21/28132 , Y10S257/90
摘要： A process is disclosed for fabricating a transistor having a channel length that is smaller than lengths resolvable using common photolithography techniques. A gate oxide layer is formed over a lightly doped semiconductor substrate. A gate conductor layer is then deposited over the gate oxide layer. The upper surface of the gate conductor layer includes a future conductor area laterally bounded by a spaced pair of target areas, wherein the lateral distance between the spaced pair of target areas is preferably chosen at the photolithography threshold. Nitrogen is implanted into the spaced pair of target areas to form a spaced pair of nitrogen bearing regions within the gate conductor layer, thereby defining a nitrogen free region in the gate conductor layer. A thermal anneal reduces the width of the nitrogen free region. A variable thickness oxide layer is then grown over the entire semiconductor topography and anisotropically etched to form an oxide mask over the reduced-width nitrogen free region. Portions of the gate conductor layer not covered by the oxide mask are then removed, leaving the reduced-width nitrogen free region as a gate conductor having a width below the photolithography threshold.
摘要翻译： 公开了一种用于制造具有小于使用普通光刻技术可分辨长度的沟道长度的晶体管的工艺。 在轻掺杂的半导体衬底上形成栅氧化层。 然后在栅极氧化物层上沉积栅极导体层。 栅极导体层的上表面包括由间隔开的一对目标区域横向限定的未来导体区域，其中间隔开的一对目标区域之间的横向距离优选地以光刻阈值选择。 将氮气注入到间隔开的一对目标区域中，以在栅极导体层内形成间隔开的一对含氮区域，从而在栅极导体层中限定无氮区域。 热退火降低了无氮区域的宽度。 然后在整个半导体拓扑上生长可变厚度的氧化物层，并进行各向异性蚀刻，以在较宽的无氮区域上形成氧化物掩模。 然后去除不被氧化物掩模覆盖的栅极导体层的部分，留下宽度窄的无氮区域作为宽度低于光刻阈值的栅极导体。
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10.发明授权Device and method for etching nitride spacers formed upon an integrated circuit gate conductor 有权用于蚀刻形成在集成电路栅极导体上的氮化物间隔物的装置和方法公开(公告)号：US06281132B1
公开(公告)日：2001-08-28
申请号：US09167622
申请日：1998-10-06
申请人： Thien T. Nguyen , Mark I. Gardner , Charles E. May
发明人： Thien T. Nguyen , Mark I. Gardner , Charles E. May
IPC分类号： H01L213065
CPC分类号： H01L21/31116
摘要： A dry etch method is presented wherein a semiconductor substrate is introduced between a first electrode and a second electrode maintained within a reaction chamber. In this method, a main etch step is performed in which a first quantity of low frequency power is applied to the pair of electrodes from an RF power source. A first gas flow is circulated through the reaction chamber during the application of power. This first gas flow includes a first argon flow, a first oxygen flow, and a first fluorocarbon flow. Applying the first quantity of low frequency power creates a first plasma for etching a portion of a nitride layer arranged above the semiconductor substrate.
摘要翻译： 提出了一种干蚀刻方法，其中将半导体衬底引入到保持在反应室内的第一电极和第二电极之间。 在该方法中，执行主要蚀刻步骤，其中从RF电源向第一对电极施加第一数量的低频功率。 在施加电力期间，第一气流在反应室中循环。 该第一气流包括第一氩气流，第一氧气流和第一碳氟化合物流。 施加第一量的低频功率产生第一等离子体，用于蚀刻布置在半导体衬底上方的氮化物层的一部分。
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