公开(公告)号：US5493667A

公开(公告)日：1996-02-20

申请号：US15541

申请日：1993-02-09

申请人： Scott B. Huck ,  Konrad K. Lai ,  Sunil R. Shenoy ,  Larry O. Smith

发明人： Scott B. Huck ,  Konrad K. Lai ,  Sunil R. Shenoy ,  Larry O. Smith

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F12/126 ,  G06F12/0864

摘要： An instruction locking apparatus and method for a cache memory allowing execution time predictability and high speed performance. The present invention implements a cache locking scheme in a two set associative instruction cache that utilizes a specially designed Least Recently Used (LRU) unit to effectively lock a first portion of the instruction cache to allow high speed and predictable execution time for time critical program code sections residing in the first portion while leaving another portion of the instruction cache free to operate as an instruction cache for other, non-critical, code sections. The present invention provides the above features in a system that is virtually transparent to the program code and does not require a variety of complex or specialized instructions or address coding methods. The present invention is flexible in that the two set associative instruction cache is transformed into what may be thought of as a static RAM in cache, and in addition, a direct map cache unit. Several different time critical code sections may be loaded and locked into the cache at different times.

摘要翻译： 一种用于缓存的指令锁定装置和方法，其允许执行时间可预测性和高速性能。 本发明在两组关联指令高速缓冲存储器中实现高速缓存锁定方案，其利用专门设计的最近使用（LRU）单元来有效地锁定指令高速缓存的第一部分，以允许用于时间关键程序代码的高速度和可预测的执行时间 驻留在第一部分中的部分，同时使指令高速缓存的另一部分可自由地作为用于其他非关键代码段的指令高速缓存。 本发明在系统中提供对程序代码实际上是透明的并且不需要各种复杂或专门的指令或地址编码方法的上述特征。 本发明的灵活性在于，将两组关联指令高速缓存转换成可以被认为是高速缓存中的静态RAM的内容，另外还有直接映射缓存单元。 可以在不同的时间将几个不同的时间关键代码段加载并锁定到高速缓存中。

公开(公告)号：US20160239304A1

公开(公告)日：2016-08-18

申请号：US14757857

申请日：2015-12-26

申请人： Martin G. Dixon ,  Ravi Rajwar ,  Konrad K. Lai ,  Robert S. Chappell ,  Rajesh S. Parthasarathy ,  Alexandre J. Farcy ,  Ilhyun Kim ,  Prakash Math ,  Matthew Merten ,  Vijaykumar Kadgi

发明人： Martin G. Dixon ,  Ravi Rajwar ,  Konrad K. Lai ,  Robert S. Chappell ,  Rajesh S. Parthasarathy ,  Alexandre J. Farcy ,  Ilhyun Kim ,  Prakash Math ,  Matthew Merten ,  Vijaykumar Kadgi

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F12/08 ,  G06F12/10 ,  G06F9/46

CPC分类号： G06F9/3855 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3859 ,  G06F9/3861 ,  G06F9/467 ,  G06F9/528 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/1045 ,  G06F13/1673 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/621 ,  G06F2212/68 ,  G06F2212/682

摘要： An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions.

摘要翻译： 本文描述了一种用于提供鲁棒的推测代码部分中止控制机制的装置和方法。 硬件能够跟踪推测性代码区域中止事件，条件和/或场景，例如显式中止指令，数据冲突，推测定时器到期，不允许的指令属性或类型等。硬件，固件，软件， 或其组合基于跟踪的中止事件进行中止判定。 作为示例，硬件可以基于一个或多个预定义事件进行初始中止确定，或者选择将事件信息传递到固件或软件处理程序以进行这种中止确定。 在确定要执行推测代码区域的中止时，硬件，固件，软件或其组合执行中止，其可以包括跟随由硬件或软件指定的回退路径。 并且为了能够测试这样的回退路径，在一个实现中，硬件为软件提供一种总是中止推测代码区域的机制。

公开(公告)号：US20150032998A1

公开(公告)日：2015-01-29

申请号：US13997243

申请日：2012-02-02

申请人： Ravi Rajwar ,  Martin G. Dixon ,  Konrad K. Lai ,  Alexandre J. Farcy ,  Bret L. Toll ,  Robert S. Chappell ,  Matthew C. Merten ,  Rajesh S. Parthasarathy ,  Per Hammarlund

发明人： Ravi Rajwar ,  Martin G. Dixon ,  Konrad K. Lai ,  Alexandre J. Farcy ,  Bret L. Toll ,  Robert S. Chappell ,  Matthew C. Merten ,  Rajesh S. Parthasarathy ,  Per Hammarlund

IPC分类号： G06F9/30

CPC分类号： G06F9/30181 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3859

摘要： An apparatus and method is described herein for providing speculation control instructions. An xAcquire and xRelease instruction are provided to define a critical section. In one embodiment, the xAcquire instruction includes a lock instruction with an elision prefix and the xRelease instruction includes a lock release instruction with an elision prefix. As a result, a processor is able to elide locks and transactionally execute a critical section defined in software by xAcquire and xRelease. But by adding only prefix hints, legacy processor are able to execute the same code by just ignoring the hints and executing the critical section traditionally with locks to guarantee mutual exclusion. Moreover, xBegin and xEnd are similarly provided for in an Instruction Set Architecture (ISA) to define a transactional code region. In addition, other control speculation instructions, such as xAbort to enable explicit abort of a critical or transactional code section and xTest to test a state of speculative execution is also provided in the ISA.

摘要翻译： 这里描述了一种用于提供猜测控制指令的装置和方法。 提供xAcquire和xRelease指令来定义关键部分。 在一个实施例中，xAcquire指令包括具有检验前缀的锁定指令，并且xRelease指令包括具有检验前缀的锁定释放指令。 因此，处理器能够通过xAcquire和xRelease来删除锁定和事务性地执行在软件中定义的关键部分。 但是通过仅添加前缀提示，传统处理器能够通过忽略提示并执行传统的锁定关键部分来保证互斥，从而执行相同的代码。 此外，xBegin和xEnd在指令集架构（ISA）中类似地提供以定义事务代码区域。 此外，还在ISA中提供了其他控制推测指令，例如xAbort，以实现关键或事务代码段的显示中止，以及xTest测试推测执行状态。

公开(公告)号：US5903738A

公开(公告)日：1999-05-11

申请号：US715049

申请日：1996-09-17

申请人： Nitin V. Sarangdhar ,  Konrad K. Lai ,  Gurbir Singh

发明人： Nitin V. Sarangdhar ,  Konrad K. Lai ,  Gurbir Singh

IPC分类号： G06F13/368 ,  G06F13/37 ,  G06F13/42 ,  G06F3/00

CPC分类号： G06F13/4213 ,  G06F13/368 ,  G06F13/37

摘要： A method and apparatus of performing bus transactions on the external bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.

摘要翻译： 一种在计算机系统的外部总线上执行总线事务的方法和装置。 本发明包括一种用于允许流水线总线系统中的无序回复的方法和装置。 无序响应包括在计算机系统中的请求代理和响应代理之间发送令牌，而不使用专用令牌总线。

公开(公告)号：US5617554A

公开(公告)日：1997-04-01

申请号：US372805

申请日：1994-12-23

申请人： Donald B. Alpert ,  Kenneth D. Shoemaker ,  Kevin C. Kahn ,  Konrad K. Lai

发明人： Donald B. Alpert ,  Kenneth D. Shoemaker ,  Kevin C. Kahn ,  Konrad K. Lai

IPC分类号： G06F12/10

CPC分类号： G06F12/1009 ,  G06F2212/652

摘要： An address translator and a method for translating a linear address into a physical address for memory management in a computer is described herein. Different memory sizes, and different page sizes can be selected. The address translator can translate from a standard 32-bit linear address for compatibility with previous 32-bit architectures, and can also translate to a physical memory size with a larger physical address than linear address; i.e., greater than 32 bits (e.g. 36 bits and up), with no increase in access time. The address translator translates a linear address that includes an offset and a plurality of fields used to select entries in a plurality of tables. The format of the linear address into fields is dependent upon the selected memory size and the selected page size. For a large memory size, the tables include a directory pointer table that includes a group of directory pointers, a plurality of page table directories each of which includes a group of page directory entries, and a plurality of page tables each of which includes a group of page table entries. The size of the entries in the tables is dependent upon the selected memory size. The contents of the tables are stored in memory, and furthermore the pointer table is stored in both main memory and in dedicated pointer table registers.

摘要翻译： 这里描述了地址转换器和用于将线性地址翻译成用于计算机中的存储器管理的物理地址的方法。 可以选择不同的内存大小和不同的页面大小。 地址转换器可以从标准的32位线性地址转换，以兼容以前的32位体系结构，并且还可以转换为具有比线性地址更大的物理地址的物理内存大小; 即大于32位（例如36位及以上），而不增加访问时间。 地址转换器翻译包括用于选择多个表中的条目的偏移和多个字段的线性地址。 线性地址到字段的格式取决于所选的内存大小和所选的页面大小。 对于大的存储器大小，表包括目录指针表，其包括一组目录指针，多个页表目录，每个页表目录包括一组页目录条目，以及多个页表，每个页表包括一组 的页表条目。 表中条目的大小取决于所选的内存大小。 表的内容存储在存储器中，此外，指针表存储在主存储器和专用指针表寄存器中。

公开(公告)号：US5550988A

公开(公告)日：1996-08-27

申请号：US205604

申请日：1994-03-01

申请人： Nitin V. Sarangdhar ,  Konrad K. Lai

发明人： Nitin V. Sarangdhar ,  Konrad K. Lai

IPC分类号： G06F11/14 ,  G06F13/36

CPC分类号： G06F13/36 ,  G06F11/1402

摘要： In a multi-processor system having a first processor, a second processor, and a bus coupling the first processor to the second processor, a method for correcting an erroneous signal corresponding to the first processor while maintaining lock atomicity. When an erroneous transaction is detected, the first processor aborts that transaction and performs a retry. On the retry, an arbitration process arbitrates between the first processor and the second processor to determine which processor is granted access to the bus. If an error is detected during the arbitration process, an arbitration re-synchronization process is initiated. In the arbitration re-synchronization process, bus requests are de-asserted and then re-arbitrated. In the re-arbitration process, the first processor initiates its request ahead of the other processor in order to maintain lock atomicity.

摘要翻译： 在具有第一处理器，第二处理器和将第一处理器耦合到第二处理器的总线的多处理器系统中，一种用于在保持锁原子性的同时校正与第一处理器相对应的错误信号的方法。 当检测到错误的事务时，第一处理器中止该事务并执行重试。 在重试时，仲裁过程在第一处理器和第二处理器之间进行仲裁以确定哪个处理器被授权访问总线。 如果在仲裁过程中检测到错误，则启动仲裁重新同步过程。 在仲裁重新同步过程中，总线请求被取消断言，然后重新仲裁。 在重新仲裁过程中，第一个处理器在另一个处理器之前发起其请求，以保持锁定原子性。

公开(公告)号：US5075848A

公开(公告)日：1991-12-24

申请号：US455585

申请日：1989-12-22

申请人： Konrad K. Lai ,  Frederick J. Pollack

发明人： Konrad K. Lai ,  Frederick J. Pollack

IPC分类号： G06F9/44 ,  G06F12/02 ,  G06F12/14

CPC分类号： G06F9/4428 ,  G06F12/1475 ,  G06F12/023 ,  G06F2216/09

摘要： An object-oriented computer architecture in which access descriptors include an object index for selecting an object in the address space, and a rights field specifying the permissible operations on a bi-paged object selected by the access descriptor. A local object lifetime bit is provided in the encoded fields portion of access descriptors, object descriptors, and page table entries to determine the lifetime of an object. The AD lifetime bit in the encoded fields of AD is compared in OTE Lifetime Check Logic with the destination object lifetime, the OTE local bit in the encoded fields of the OTE access descriptor. The OTE local bit in the encoded fields of the OTE is compared in PDTE Lifetime Check Logic with the destination object lifetime, the PDTE local bit in the encoded fields of the PDTE access descriptor. The PDTE local bit in the encoded fields of the PDTE is compared in PTE Lifetime Check Logic with the destination object lifetime, the PTE local bit in the encoded fields of the PTE access descriptor. If any of these checks fails, a protection lifetime fault is asserted.

摘要翻译： 一种面向对象的计算机体系结构，其中访问描述符包括用于选择地址空间中的对象的对象索引，以及权限字段，其指定由访问描述符选择的双页对象的允许操作。 在访问描述符，对象描述符和页表项的编码字段部分中提供本地对象生存期，以确定对象的生命周期。 在OTE生命周期校验逻辑与目标对象寿命（OTE访问描述符的编码字段中的OTE本地位）比较AD的编码字段中的AD生存位。 OTE的编码字段中的OTE本地位在PDTE Lifetime Check Logic中与目标对象生命周期（PDTE访问描述符的编码字段中的PDTE本地位）进行比较。 PDTE的编码字段中的PDTE本地位在PTE终生校验逻辑中与目标对象生命周期（PTE访问描述符的编码字段中的PTE本地位）进行比较。 如果这些检查中有任何一个失败，则保护生命周期故障被断言。

公开(公告)号：US20160132336A1

公开(公告)日：2016-05-12

申请号：US14998276

申请日：2015-12-26

申请人： Martin G. Dixon ,  Ravi Rajwar ,  Konrad K. Lai ,  Robert S. Chappell ,  Rajesh S. Parthasarathy ,  Alexandre J. Farcy ,  Ilhyun Kim ,  Prakash Math ,  Matthew Merten ,  Vijaykumar Kadgi

发明人： Martin G. Dixon ,  Ravi Rajwar ,  Konrad K. Lai ,  Robert S. Chappell ,  Rajesh S. Parthasarathy ,  Alexandre J. Farcy ,  Ilhyun Kim ,  Prakash Math ,  Matthew Merten ,  Vijaykumar Kadgi

IPC分类号： G06F9/30 ,  G06F12/08 ,  G06F13/42 ,  G06F13/16 ,  G06F13/40

CPC分类号： G06F9/3855 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3859 ,  G06F9/3861 ,  G06F9/467 ,  G06F9/528 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/1045 ,  G06F13/1673 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/621 ,  G06F2212/68 ,  G06F2212/682

摘要： An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions.

公开(公告)号：US08972994B2

公开(公告)日：2015-03-03

申请号：US12645668

申请日：2009-12-23

申请人： Suresh Srinivas ,  Stephen H. Dohrmann ,  Mingqiu Sun ,  Uma Srinivasan ,  Ravi Rajwar ,  Konrad K. Lai

发明人： Suresh Srinivas ,  Stephen H. Dohrmann ,  Mingqiu Sun ,  Uma Srinivasan ,  Ravi Rajwar ,  Konrad K. Lai

IPC分类号： G06F9/44 ,  G06F9/46 ,  G06F9/52 ,  G06F9/455 ,  G06F17/30 ,  G06F9/38 ,  G06F9/45

CPC分类号： G06F9/528 ,  G06F8/458 ,  G06F9/3842 ,  G06F9/45516 ,  G06F9/526 ,  G06F17/30168 ,  G06F17/30362 ,  Y10S707/99938

摘要： Example methods and apparatus to manage object locks are disclosed. A disclosed example method includes receiving an object lock request from a processor, the lock request associated with object lock code to lock an object, and generating object lock-bypass code based on a type of the processor, the object lock-bypass code to execute in a managed runtime in response to receiving the object lock request. The example method also includes identifying a type of instruction set architecture (ISA) associated with the processor, invoking a checkpoint instruction for the processor based on the identified ISA, suspending the object lock code from executing and executing target code when the object is uncontended, and allowing the object lock code to execute when the object is contended.

摘要翻译： 公开了用于管理对象锁的示例性方法和装置。 所公开的示例性方法包括从处理器接收对象锁定请求，与对象锁定代码相关联的锁定请求以锁定对象，以及基于处理器的类型生成对象锁定旁路代码，执行对象锁定旁路代码 在受管运行时响应于接收到对象锁定请求。 示例性方法还包括识别与处理器相关联的指令集架构（ISA）的类型，基于所识别的ISA调用处理器的检查点指令，当对象不受约束时暂停对象锁定代码执行和执行目标代码， 并允许对象锁定代码在对象被竞争时执行。

公开(公告)号：US20140379996A1

公开(公告)日：2014-12-25

申请号：US13997245

申请日：2012-02-02

申请人： Ravi Rajwar ,  Martin G. Dixon ,  Konrad K. Lai ,  Robert S. Chappell ,  Bret L. Toll

发明人： Ravi Rajwar ,  Martin G. Dixon ,  Konrad K. Lai ,  Robert S. Chappell ,  Bret L. Toll

IPC分类号： G06F9/52 ,  G06F12/08 ,  G06F9/46

摘要： An apparatus and method is described herein for providing speculative escape instructions. Specifically, an explicit non-transactional load operation is described herein. During execution of a speculative code region (e.g. a transaction or critical section) loads are normally tracked in a read set. However, a programmer or compiler may utilize the explicit non-transactional read to load from a memory address into a destination register, while not adding the read/load to the transactional read set. Similarly, a non-transactional store is also provided. Here, a transactional store is performed and not added to a write set during speculative code execution. And the store may be immediately globally visible and/or persistent (even after an abort of the speculative code region). In other words, speculative escape operations are provided to ‘escape’ a speculative code region to perform non-transactional memory accesses without causing the speculative code region to abort or fail.

摘要翻译： 这里描述了一种用于提供推测逃逸指令的装置和方法。 具体地，本文描述了显式的非事务性加载操作。 在推测性代码区域（例如交易或关键部分）的执行期间，通常在读取集合中跟踪负载。 然而，程序员或编译器可以利用显式的非事务性读取从存储器地址加载到目标寄存器中，而不将读取/加载添加到事务读取集合。 同样，也提供非事务存储。 这里，在推测性代码执行期间执行事务存储并且不添加到写入集合。 并且商店可能立即全局可见和/或持久（即使在推测性代码区域中止之后）。 换句话说，提供推测性逃避操作以“逃逸”推测性代码区域以执行非事务性存储器访问，而不会导致推测性代码区域中止或失败。