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    Method and imaging apparatus for imaging a structure onto a semiconductor wafer by means of immersion lithography
    1.
    发明授权
    Method and imaging apparatus for imaging a structure onto a semiconductor wafer by means of immersion lithography 有权
    用于通过浸没式光刻将结构成像到半导体晶片上的方法和成像装置

    公开(公告)号：US07224439B2

    公开(公告)日：2007-05-29

    申请号：US10986288

    申请日：2004-11-12

    申请人： Martin Verhoeven ,  Thomas Zell

    发明人： Martin Verhoeven ,  Thomas Zell

    IPC分类号： G03B27/43

    CPC分类号： G03F7/70075 ,  G03B27/52 ,  G03F7/70091 ,  G03F7/70341

    摘要： The hydrodynamic effects—which occur during immersion lithography as a result of the movement of the semiconductor wafer—in a liquid preferably provided between the last lens surface of the projection system and the semiconductor wafer can be avoided by means of a movable illumination region for illuminating a cutout of a mask containing a structure to that can be imaged onto the semiconductor wafer. A scan movement of the mask and the semiconductor wafer can be either reduced or entirely avoided by means of a movement of the illumination region.

    摘要翻译： 作为半导体晶片移动的结果，在优选设置在投影系统的最后一个透镜表面之间的液体和半导体晶片之间的液体中的流体动力学效应可以通过用于照明的可移动照明区域来避免 包含可以成像到半导体晶片上的结构的掩模的切口。 可以通过照明区域的移动来减少或完全避免掩模和半导体晶片的扫描移动。

    Method and imaging apparatus for imaging a structure onto a semiconductor wafer by means of immersion lithography
    2.
    发明申请
    Method and imaging apparatus for imaging a structure onto a semiconductor wafer by means of immersion lithography 有权
    用于通过浸没式光刻将结构成像到半导体晶片上的方法和成像装置

    公开(公告)号：US20050117135A1

    公开(公告)日：2005-06-02

    申请号：US10986288

    申请日：2004-11-12

    申请人： Martin Verhoeven ,  Thomas Zell

    发明人： Martin Verhoeven ,  Thomas Zell

    IPC分类号： G03B27/52 ,  G03F7/20 ,  G03F7/22

    CPC分类号： G03F7/70075 ,  G03B27/52 ,  G03F7/70091 ,  G03F7/70341

    摘要： The hydrodynamic effects—which occur during immersion lithography as a result of the movement of the semiconductor wafer—in a liquid preferably provided between the last lens surface of the projection system and the semiconductor wafer can be avoided by means of a movable illumination region for illuminating a cutout of a mask containing a structure to that can be imaged onto the semiconductor wafer. A scan movement of the mask and the semiconductor wafer can be either reduced or entirely avoided by means of a movement of the illumination region.

    摘要翻译： 作为半导体晶片移动的结果，在优选设置在投影系统的最后一个透镜表面之间的液体和半导体晶片之间的液体中的流体动力学效应可以通过用于照明的可移动照明区域来避免 包含可以成像到半导体晶片上的结构的掩模的切口。 可以通过照明区域的移动来减少或完全避免掩模和半导体晶片的扫描移动。

    Compensation of Process-Induced Displacement
    4.
    发明申请
    Compensation of Process-Induced Displacement 审中-公开
    过程引起的位移补偿

    公开(公告)号：US20100040983A1

    公开(公告)日：2010-02-18

    申请号：US12191492

    申请日：2008-08-14

    申请人： Heinrich Ollendorf ,  Thomas Zell ,  Michael Kubis ,  Steffen Schmidt ,  Elke Hietschold

    发明人： Heinrich Ollendorf ,  Thomas Zell ,  Michael Kubis ,  Steffen Schmidt ,  Elke Hietschold

    IPC分类号： G03F7/20

    CPC分类号： G03F1/72

    摘要： A method of manufacturing integrated circuits includes determining a process-induced displacement (e.g., a stress-induced displacement) between primary structures on a substrate and providing a photomask with mask features assigned to the primary structures. The distances between the mask features are set such that the process-induced displacement is compensated.

    摘要翻译： 制造集成电路的方法包括确定衬底上的主要结构之间的过程引起的位移（例如，应力引起的位移），并提供具有分配给主要结构的掩模特征的光掩模。 掩模特征之间的距离被设置为使得处理引起的位移被补偿。

    Stacked via with specially designed landing pad for integrated semiconductor structures
    5.
    发明授权
    Stacked via with specially designed landing pad for integrated semiconductor structures 有权
    通过专门设计的集成半导体结构的着陆垫进行堆叠

    公开(公告)号：US06737748B2

    公开(公告)日：2004-05-18

    申请号：US10082554

    申请日：2002-02-25

    申请人： Lothar Bauch ,  Thomas Zell ,  Matthias Uwe Lehr ,  Albrecht Kieslich

    发明人： Lothar Bauch ,  Thomas Zell ,  Matthias Uwe Lehr ,  Albrecht Kieslich

    IPC分类号： H01L2348

    CPC分类号： H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In the fabrication of stacked vias, metal islands referred to as landing pads are introduced for the purpose of contact-connection between the vias that are arranged one above the other. The metal islands project laterally beyond the vias to a significant extent on account of the line shortening effect. The vias arranged in layers lying one above the other are laterally offset with respect to one another. The landing pad of the invention is configured as an interconnect running between the vias. On account of the line shortening effect, which is less critical for longer tracks, contact areas provided at the ends of the interconnect do not have to be chosen to be as large as the square contact areas of conventional metal islands and can therefore be accommodated to save more space on a circuit layout to be miniaturized. The shrink factor of such a semiconductor structure is increased.

    摘要翻译： 在堆叠过孔的制造中，引入了称为着陆焊盘的金属岛，用于在彼此上下布置的通孔之间的接触连接的目的。 由于线路缩短效应，金属岛在很大程度上突出超出通孔。 布置在一个彼此上下的层中的通孔相对于彼此横向偏移。 本发明的着陆垫被配置为在通孔之间运行的互连。 由于对较长轨道不那么关键的线路缩短效应，互连端部设置的接触区域不必被选择为与常规金属岛的方形接触面积一样大，因此可以容纳到 节省电路布局上的更多空间以实现小型化。 这种半导体结构的收缩率增加。