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    Test mode method and apparatus for internal memory timing signals
    1.
    发明授权
    Test mode method and apparatus for internal memory timing signals 有权
    用于内部存储器定时信号的测试模式方法和装置

    公开(公告)号：US07339841B2

    公开(公告)日：2008-03-04

    申请号：US11227099

    申请日：2005-09-16

    申请人： Martin Versen ,  Klaus Nierle ,  Oliver Kiehl ,  Ernst Stahl

    发明人： Martin Versen ,  Klaus Nierle ,  Oliver Kiehl ,  Ernst Stahl

    IPC分类号： G11C7/00

    CPC分类号： G11C29/50 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/50012

    摘要： A method of testing internal signals of a memory for timing marginalities which may result in unstable operation includes: delaying internal address signals of the memory by an amount great enough so that data cannot be validly written to and read from memory locations which are accessed by address signals having timing marginalities which are delayed but small enough so that data can be validly written to and read from memory locations which are accessed by address signals not having such timing marginalities which are delayed. Data is then written to and read from memory locations which are accessed by delayed address signals, and a determination is made as to whether the data read from any memory location does not correspond with the data written to such memory location.

    摘要翻译： 测试存储器的内部信号的方法，其可能导致不稳定的操作的定时边界，包括：将存储器的内部地址信号延迟足够大的量，使得数据不能被有效地写入到存储器位置并从其被地址访问的存储器位置读取 具有延迟但足够小的定时边缘的信号，使得数据可以被有效地写入到存储单元中并从存储位置读取，地址信号不具有被延迟的这种定时边缘。 然后将数据写入到由延迟的地址信号访问的存储器位置并从其读取，并且确定从任何存储器位置读取的数据是否与写入该存储器位置的数据不对应。

    Test mode method and apparatus for internal memory timing signals
    2.
    发明申请
    Test mode method and apparatus for internal memory timing signals 有权
    用于内部存储器定时信号的测试模式方法和装置

    公开(公告)号：US20070064505A1

    公开(公告)日：2007-03-22

    申请号：US11227099

    申请日：2005-09-16

    申请人： Martin Versen ,  Klaus Nierle ,  Oliver Kiehl ,  Ernst Stahl

    发明人： Martin Versen ,  Klaus Nierle ,  Oliver Kiehl ,  Ernst Stahl

    IPC分类号： G11C7/00

    CPC分类号： G11C29/50 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/50012

    摘要： A method of testing internal signals of a memory for timing marginalities which may result in unstable operation includes: delaying internal address signals of the memory by an amount great enough so that data cannot be validly written to and read from memory locations which are accessed by address signals having timing marginalities which are delayed but small enough so that data can be validly written to and read from memory locations which are accessed by address signals not having such timing marginalities which are delayed. Data is then written to and read from memory locations which are accessed by delayed address signals, and a determination is made as to whether the data read from any memory location does not correspond with the data written to such memory location.

    摘要翻译： 测试存储器的内部信号的方法，其可能导致不稳定的操作的定时边界，包括：将存储器的内部地址信号延迟足够大的量，使得数据不能被有效地写入到存储器位置并从其被地址访问的存储器位置读取 具有延迟但足够小的定时边缘的信号，使得数据可以被有效地写入到存储单元中并从存储位置读取，地址信号不具有被延迟的这种定时边缘。 然后将数据写入到由延迟的地址信号访问的存储器位置并从其读取，并且确定从任何存储器位置读取的数据是否与写入该存储器位置的数据不对应。

    Chip specific test mode execution on a memory module
    3.
    发明申请
    Chip specific test mode execution on a memory module 审中-公开
    在内存模块上执行芯片特定的测试模式

    公开(公告)号：US20070094554A1

    公开(公告)日：2007-04-26

    申请号：US11253716

    申请日：2005-10-20

    申请人： Martin Versen ,  Oliver Kiehl

    发明人： Martin Versen ,  Oliver Kiehl

    IPC分类号： G11C29/00

    CPC分类号： G11C29/46 ,  G11C5/04 ,  G11C2029/4402

    摘要： A test mode for component-specific testing of a memory module. Data is written to and stored in each memory component of a memory module, which data indicates whether the memory component is to execute a particular test mode. Upon receiving a test mode command supplied in common to all of the memory components on the memory module, each memory component examines the data to determine whether it is to execute a test mode command supplied contemporaneously therewith or subsequently supplied test mode commands.

    摘要翻译： 用于内存模块组件特定测试的测试模式。 将数据写入并存储在存储器模块的每个存储器组件中，该数据指示存储器组件是否要执行特定的测试模式。 在接收到对存储器模块中的所有存储器组件共同提供的测试模式命令时，每个存储器组件检查数据以确定是否执行与其同时提供的测试模式命令或随后提供的测试模式命令。

    Semiconductor package and method
    4.
    发明授权
    Semiconductor package and method 失效
    半导体封装及方法

    公开(公告)号：US06730989B1

    公开(公告)日：2004-05-04

    申请号：US09596130

    申请日：2000-06-16

    申请人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

    发明人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

    IPC分类号： H01L23544

    CPC分类号： H01L23/5382 ,  H01L23/50 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.

    摘要翻译： 半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。 半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。 晶片的分数部分具有电连接到芯片的多个电触点。 封装还包括其上具有电导体的电介质构件。 电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。 提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。

    Multiple chip semiconductor arrangement having electrical components in separating regions
    5.
    发明授权
    Multiple chip semiconductor arrangement having electrical components in separating regions 有权
    在分离区域中具有电气部件的多芯片半导体布置

    公开(公告)号：US06815803B1

    公开(公告)日：2004-11-09

    申请号：US09596129

    申请日：2000-06-16

    申请人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

    发明人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

    IPC分类号： H01L23544

    CPC分类号： H01L25/18 ,  H01L23/50 ,  H01L23/5382 ,  H01L27/105 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.

    摘要翻译： 半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。 半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。 晶片的分数部分具有电连接到芯片的多个电触点。 封装还包括其上具有电导体的电介质构件。 电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。 提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。

    Multiple chip semiconductor arrangement having electrical components in separating regions
    6.
    发明授权
    Multiple chip semiconductor arrangement having electrical components in separating regions 失效
    在分离区域中具有电气部件的多芯片半导体布置

    公开(公告)号：US07060529B2

    公开(公告)日：2006-06-13

    申请号：US10841162

    申请日：2004-05-07

    申请人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

    发明人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

    IPC分类号： H01L21/50 ,  H01L21/30

    CPC分类号： H01L25/18 ,  H01L23/50 ,  H01L23/5382 ,  H01L27/105 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.

    摘要翻译： 半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。 半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。 晶片的分数部分具有电连接到芯片的多个电触点。 封装还包括其上具有电导体的电介质构件。 电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。 提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。

    Data transmission system with reduced power consumption
    10.
    发明授权
    Data transmission system with reduced power consumption 有权
    数据传输系统功耗降低

    公开(公告)号：US07321628B2

    公开(公告)日：2008-01-22

    申请号：US10674859

    申请日：2003-09-30

    申请人： Oliver Kiehl

    发明人： Oliver Kiehl

    IPC分类号： H04L27/00

    CPC分类号： H04L25/4915

    摘要： System and method for reducing power consumption and noise in a transmission system with an asymmetrically terminated transmission line. A preferred embodiment comprises encoding data words to reduce the number of times a given state appears in a code word. The preferred embodiment comprises counting the number of times a given state appears in a data word. If the count is greater than half of the total number of bits in the data word, then the data word is inverted and a weight bit can be set to the given state. If the count is less than (or equal to) half of the total number of bits, then the data word may be unchanged and the weight bit can be set to the inverse of the given state. The code word can be generated by appending the weight bit to the data word.

    摘要翻译： 具有不对称端接传输线的传输系统中降低功耗和噪声的系统和方法。 优选实施例包括编码数据字以减少给定状态在码字中出现的次数。 优选实施例包括对给定状态在数据字中出现的次数进行计数。 如果计数大于数据字中总位数的一半，则数据字被反转，并且可以将权重位设置为给定状态。 如果计数小于（或等于）总位数的一半，则数据字可以不变，并且权重位可以被设置为给定状态的倒数。 可以通过将权重位附加到数据字来生成代码字。