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公开(公告)号：US20110181308A1
公开(公告)日：2011-07-28
申请号：US13062937
申请日：2009-09-03
CPC分类号： G11C29/56 , G01R31/31721 , G11C29/12005 , G11C2029/5602
摘要： A main power supply supplies a power supply voltage to a power supply terminal of a DUT. A control pattern generator generates a control pattern including a pulse sequence. A compensation circuit intermittently injects a compensation current to the power supply terminal of the DUT via a path different from that of the main power supply. A switch is arranged between an output terminal of a voltage source and the power supply terminal of the DUT, and is turned on and off according to the control pattern.
摘要翻译： 主电源向DUT的电源端提供电源电压。 控制模式发生器产生包括脉冲序列的控制模式。 补偿电路通过与主电源不同的路径间歇地向DUT的电源端子注入补偿电流。 开关设置在电压源的输出端子和DUT的电源端子之间，并且根据控制模式被导通和截止。
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公开(公告)号：US08933716B2
公开(公告)日：2015-01-13
申请号：US13062937
申请日：2009-09-03
IPC分类号： G11C29/56 , G01R31/317 , G11C29/12
CPC分类号： G11C29/56 , G01R31/31721 , G11C29/12005 , G11C2029/5602
摘要： A main power supply supplies a power supply voltage to a power supply terminal of a DUT. A control pattern generator generates a control pattern including a pulse sequence. A compensation circuit intermittently injects a compensation current to the power supply terminal of the DUT via a path different from that of the main power supply. A switch is arranged between an output terminal of a voltage source and the power supply terminal of the DUT, and is turned on and off according to the control pattern.
摘要翻译： 主电源向DUT的电源端提供电源电压。 控制模式发生器产生包括脉冲序列的控制模式。 补偿电路通过与主电源不同的路径间歇地向DUT的电源端子注入补偿电流。 开关设置在电压源的输出端子和DUT的电源端子之间，并且根据控制模式被导通和截止。
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公开(公告)号：US07684944B2
公开(公告)日：2010-03-23
申请号：US11582143
申请日：2006-10-17
申请人： Masahiro Ishida , Toshiyuki Okayasu
发明人： Masahiro Ishida , Toshiyuki Okayasu
IPC分类号： G06F19/00
CPC分类号： G01R35/00 , G01R31/31709
摘要： There is provided a calibration apparatus that calibrates a jitter measuring circuit for outputting a jitter measuring signal with a level according to an amount of jitter in an input signal based on the input signal and a delay signal obtained by delaying the input signal by means of a variable delay circuit. The calibration apparatus includes a delay control section that sequentially sets a first delay amount and a second delay amount in the variable delay circuit and a gain computing section that computes gain in the jitter measuring circuit based on the jitter measuring signal respectively output from the jitter measuring circuit for the first delay amount and the second delay amount.
摘要翻译： 提供一种校准装置，其校准抖动测量电路，用于基于输入信号输出具有根据输入信号中的抖动量的电平的抖动测量信号，以及通过延迟输入信号获得的延迟信号 可变延迟电路。 校准装置包括延迟控制部分，其顺序地设置可变延迟电路中的第一延迟量和第二延迟量;以及增益计算部分，其基于从抖动测量分别输出的抖动测量信号来计算抖动测量电路中的增益 电路，用于第一延迟量和第二延迟量。
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公开(公告)号：US20130147499A1
公开(公告)日：2013-06-13
申请号：US13316373
申请日：2011-12-09
IPC分类号： G01R31/00
CPC分类号： G01R31/31924
摘要： A pattern generator generates a pattern signal which represents a test signal to be supplied to a DUT. A driver generates a test signal having a level that corresponds to the pattern signal, and outputs the test signal thus generated to the DUT. A voltage modulator changes, in a predetermined voltage range, the voltage level of the test signal output from the driver DR.
摘要翻译： 模式发生器产生表示要提供给DUT的测试信号的模式信号。 驱动器产生具有对应于模式信号的电平的测试信号，并且将如此产生的测试信号输出到DUT。 电压调制器在预定电压范围内改变从驱动器DR输出的测试信号的电压电平。
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公开(公告)号：US08896332B2
公开(公告)日：2014-11-25
申请号：US13316373
申请日：2011-12-09
CPC分类号： G01R31/31924
摘要： A pattern generator generates a pattern signal which represents a test signal to be supplied to a DUT. A driver generates a test signal having a level that corresponds to the pattern signal, and outputs the test signal thus generated to the DUT. A voltage modulator changes, in a predetermined voltage range, the voltage level of the test signal output from the driver DR.
摘要翻译： 模式发生器产生表示要提供给DUT的测试信号的模式信号。 驱动器产生具有对应于模式信号的电平的测试信号，并且将如此产生的测试信号输出到DUT。 电压调制器在预定电压范围内改变从驱动器DR输出的测试信号的电压电平。
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公开(公告)号：US20120146416A1
公开(公告)日：2012-06-14
申请号：US13311356
申请日：2011-12-05
IPC分类号： H02J1/10
CPC分类号： G01R31/31924 , Y10T307/505
摘要： A DUT comprises a notifying circuit configured to generate a notification signal which is used to notify an external circuit of an event that leads to a change in the operating current of the DUT before such an event occurs. A main power supply supplies electric power to a power supply terminal of the DUT. A power supply compensation circuit comprises a switch element which is controlled according to a control signal, and is configured to generate a compensation pulse current according to the on/off state of the switch element. A compensation control circuit receives the notification signal from the DUT, and outputs, to the power supply compensation circuit, a control signal which is used to control the switch element, and which is generated based upon at least the notification signal.
摘要翻译： DUT包括通知电路，其被配置为产生通知信号，该通知信号用于在事件发生之前通知外部电路导致DUT的工作电流变化的事件。 主电源向DUT的电源端供电。 电源补偿电路包括根据控制信号控制的开关元件，并且被配置为根据开关元件的接通/断开状态产生补偿脉冲电流。 补偿控制电路接收来自DUT的通知信号，并且向电源补偿电路输出用于控制开关元件的控制信号，并且至少基于通知信号生成控制信号。
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公开(公告)号：US20120112783A1
公开(公告)日：2012-05-10
申请号：US13287950
申请日：2011-11-02
IPC分类号： G01R31/26
CPC分类号： G01R31/318511 , G01R31/31721 , G11C29/56004 , G11C2029/5602
摘要： A test apparatus tests a DUT formed on a wafer. A power supply compensation circuit includes source and a sink switches each controlled according to a control signal. When the source or sink switch is turned on, a compensation pulse current is generated, and the compensation pulse current is injected into a power supply terminal of the DUT via a path that differs from that of a main power supply, or is drawn from the power supply current that flows from the main power supply to the DUT via a path that differs from that of the power supply terminal of the DUT. Of components forming the power supply compensation circuit, including the source and sink switches, a part is formed on the wafer. Pads are formed on the wafer in order to apply a signal to such a part of the power supply compensation circuit formed on the wafer.
摘要翻译： 测试设备测试在晶片上形成的DUT。 电源补偿电路包括根据控制信号控制的源和宿开关。 当源极或吸收开关导通时，产生补偿脉冲电流，并且补偿脉冲电流通过与主电源的路径不同的路径注入DUT的电源端子，或者从 通过不同于DUT的电源端子的路径从主电源流向DUT的电源电流。 构成电源补偿电路的部件，包括源极和漏极开关，在晶片上形成一部分。 在晶片上形成衬垫以便向形成在晶片上的电源补偿电路的这一部分施加信号。
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公开(公告)号：US20110054827A1
公开(公告)日：2011-03-03
申请号：US12548399
申请日：2009-08-26
IPC分类号： G06F19/00
CPC分类号： G01R31/31917 , G01R31/31706 , G01R31/31932
摘要： A test apparatus tests a modulated signal under test received from a DUT. A cross timing data generating unit generates cross timing data which indicates a timing at which the level of the signal under test crosses each of multiple thresholds. An expected value data generating unit generates timing expected value data which indicates a timing at which an expected value waveform of the signal under test crosses each of the multiple thresholds when the expected value waveform is compared with each of the multiple thresholds. A timing comparison unit compares the cross timing data with the timing expected value data.
摘要翻译： 一个测试设备测试从DUT接收的被测信号。 交叉定时数据生成单元生成交叉定时数据，该交叉定时数据指示被测信号的电平与多个阈值中的每个阈值相交的定时。 期望值数据生成单元生成定时期望值数据，其指示当将期望值波形与多个阈值中的每一个进行比较时，被测信号的预期值波形与多个阈值中的每一个相交的定时。 定时比较单元将交叉定时数据与定时预期值数据进行比较。
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公开(公告)号：US20080091371A1
公开(公告)日：2008-04-17
申请号：US11582143
申请日：2006-10-17
申请人： Masahiro Ishida , Toshiyuki Okayasu
发明人： Masahiro Ishida , Toshiyuki Okayasu
IPC分类号： G06F19/00
CPC分类号： G01R35/00 , G01R31/31709
摘要： There is provided a calibration apparatus that calibrates a jitter measuring circuit for outputting a jitter measuring signal with a level according to an amount of jitter in an input signal based on the input signal and a delay signal obtained by delaying the input signal by means of a variable delay circuit. The calibration apparatus includes a delay control section that sequentially sets a first delay amount and a second delay amount in the variable delay circuit and a gain computing section that computes gain in the jitter measuring circuit based on the jitter measuring signal respectively output from the jitter measuring circuit for the first delay amount and the second delay amount.
摘要翻译： 提供一种校准装置，其校准抖动测量电路，用于基于输入信号输出具有根据输入信号中的抖动量的电平的抖动测量信号，以及通过延迟输入信号获得的延迟信号 可变延迟电路。 校准装置包括延迟控制部分，其顺序地设置可变延迟电路中的第一延迟量和第二延迟量;以及增益计算部分，其基于从抖动测量分别输出的抖动测量信号来计算抖动测量电路中的增益 电路，用于第一延迟量和第二延迟量。
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公开(公告)号：US20100259435A1
公开(公告)日：2010-10-14
申请号：US12745350
申请日：2008-12-02
CPC分类号： H03K5/14 , G01R19/2506 , G04F10/005 , H01L2924/0002 , H03K3/0315 , H03K5/15046 , H03K5/1508 , H03L7/0812 , H03M1/207 , H03M1/502 , H01L2924/00
摘要： A delay circuit includes a MOSFET and bias voltage sources. The bias voltage sources apply a voltage difference between the drain and source of the MOSFET. The bias voltage source supplies a source voltage to a source electrode of the MOSFET. The bias voltage source supplies a drain voltage to a drain electrode of the MOSFET. An input signal to be delayed is propagated through the gate of the MOSFET in the gate width direction (y-axis direction).
摘要翻译： 延迟电路包括MOSFET和偏置电压源。 偏置电压源施加MOSFET的漏极和源极之间的电压差。 偏置电压源将源极电压提供给MOSFET的源极。 偏置电压源将漏极电压提供给MOSFET的漏极。 要延迟的输入信号在栅极宽度方向（y轴方向）上通过MOSFET的栅极传播。
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