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    Semiconductor integrated circuit with a test circuit for input buffer threshold
    5.
    发明授权
    Semiconductor integrated circuit with a test circuit for input buffer threshold 失效
    半导体集成电路具有输入缓冲阈值的测试电路

    公开(公告)号：US5633599A

    公开(公告)日：1997-05-27

    申请号：US509616

    申请日：1995-07-31

    申请人： Shuji Kubota

    发明人： Shuji Kubota

    IPC分类号： G01R31/26 ,  G01R31/28 ,  G01R31/30 ,  G01R31/317 ,  H01L21/8238 ,  H01L27/092 ,  H03K19/003

    CPC分类号： G01R31/31715 ,  G01R31/3004 ,  G01R31/31712

    摘要： In a semiconductor integrated circuit provided with a circuit for testing an input buffer threshold voltage, an output node of a first logic gate having its output logic value determined by an output signal of an input buffer, and an output node of a second logic gate having its output logic value determined by a condition setting signal from an external source, are connected to a common signal line. When a standardized voltage for discriminating the threshold voltage is applied to the input buffer, if the input buffer malfunctions, the output signal of the first logic gate collides with the output signal of the second logic gate on the common signal line, so that a power supply current greatly increases.

    摘要翻译： 在设置有用于测试输入缓冲器阈值电压的电路的半导体集成电路中，具有由输入缓冲器的输出信号确定的其输出逻辑值的第一逻辑门的输出节点和具有第二逻辑门的​​输出节点， 其由来自外部源的条件设置信号确定的输出逻辑值连接到公共信号线。 当用于识别阈值电压的标准化电压被施加到输入缓冲器时，如果输入缓冲器发生故障，则第一逻辑门的输出信号与公共信号线上的第二逻辑门的​​输出信号相冲突，使得功率 电源电流大大增加。

    Error correcting coder/decoder
    6.
    发明授权
    Error correcting coder/decoder 失效
    错误校正编码器/解码器

    公开(公告)号：US4805174A

    公开(公告)日：1989-02-14

    申请号：US947328

    申请日：1986-12-29

    申请人： Shuji Kubota ,  Shuzo Kato

    发明人： Shuji Kubota ,  Shuzo Kato

    IPC分类号： H04B14/04 ,  H03M13/23 ,  H03M13/41 ,  H04L27/18 ,  G06F11/10

    CPC分类号： H03M13/41 ,  H03M13/23

    摘要： This invention relates to a convolutional encoder which encodes original data into convolutional codes by using a multinomial from which predetermined terms of the generation multinomial for generating the original convolutional codes are eliminated to thereby achieve high transmission efficiency as well as high error correcting capacity. The maximum likelihood decoder which is provided on the receiver side to correspond to the encoder can decode in maximum likelihood by calculating the branch metrics of received encoded data and decode the original data in correspondence to the coding rate of the original data with those branch metrics.

    摘要翻译： 卷积编码器本发明涉及一种卷积编码器，其通过使用多项式将原始数据编码为卷积码，消除了用于产生原始卷积码的生成多项式的预定项，从而实现高传输效率以及高纠错能力。 提供在接收机侧以对应于编码器的最大似然解码器可以通过计算接收到的编码数据的分支度量并以与这些分支度量的原始数据的编码率对应的原始数据来解码最大似然。

    Error control coding arrangement for digital communications system
    7.
    发明授权
    Error control coding arrangement for digital communications system 失效
    数字通信系统的错误控制编码方案

    公开(公告)号：US5384809A

    公开(公告)日：1995-01-24

    申请号：US184341

    申请日：1993-12-23

    申请人： Toshiharu Yagi ,  Shuzo Kato ,  Shuji Kubota

    发明人： Toshiharu Yagi ,  Shuzo Kato ,  Shuji Kubota

    IPC分类号： H04L27/22 ,  H04L1/00 ,  H04L27/34 ,  H04L27/00

    CPC分类号： H04L1/0052 ,  H04L1/0043 ,  H04L1/0054 ,  H04L1/0059 ,  H04L1/0066 ,  H04L27/3433

    摘要： A serial-parallel converter is arranged to convert an information sequence into a plurality of bit sequences. Two convolutional encoders are provided which respectively receive bit sequences from the serial-parallel converter. Each of the two convolutional encoders outputs first and second bit sequences. First parallel-serial converter receives the first bit sequences and converts them into third bit sequence, while second parallel-serial converter receives the second bit sequences and converts them into fourth bit sequence. The third and fourth bit sequences are used to modulate two carriers with a phase difference of .pi./2 radians.

    摘要翻译： 串行并行转换器被布置成将信息序列转换成多个比特序列。 提供两个卷积编码器，分别从串行 - 并行转换器接收比特序列。 两个卷积编码器中的每一个输出第一和第二比特序列。 第一并行串行转换器接收第一比特序列并将其转换成第三比特序列，而第二并行 - 串行转换器接收第二比特序列并将它们转换成第四比特序列。 第三和第四位序列用于调制具有π/ 2弧度相位差的两个载波。

    Method and circuit for decoding convolutional codes
    8.
    发明授权
    Method and circuit for decoding convolutional codes 失效
    用于解码卷积码的方法和电路

    公开(公告)号：US5327441A

    公开(公告)日：1994-07-05

    申请号：US991215

    申请日：1992-12-15

    申请人： Katsuhiko Kawazoe ,  Shunji Honda ,  Shuji Kubota ,  Shuzo Kato

    发明人： Katsuhiko Kawazoe ,  Shunji Honda ,  Shuji Kubota ,  Shuzo Kato

    IPC分类号： H04L25/08 ,  H03M13/23 ,  H03M13/41 ,  G06F11/10

    CPC分类号： H03M13/6502 ,  H03M13/23 ,  H03M13/41

    摘要： In a simple decoder which decodes convolutional codes of constraint length K and coding rate n/m, encoded data which is supplied thereto in steps of m bits are distributed, bit by bit, to m shift registers each having x=[(K-1)/(m-n)] series-connected shift stages. Here, [p] means the minimum integer equal to or larger than a real number p. The connection of n modulo-2 addition circuits to all the shift stages of all the shift registers is defined by n decoding generative vectors which define n decoding generative polynomials. The modulo-2 addition circuits perform modulo-2 additions of the outputs of the shift stages connected thereto and output n results of additions as decoded results of n bits. The n decoding generative vectors are selected from decoding generative vectors of N rows which are obtained as an inverse matrix of a square matrix whose elements are N.times.N coefficients which define N=mx convolutional code generating polynomials.

    摘要翻译： 在解码约束长度K和编码率n / m的卷积码的简单解码器中，以m比特为单位提供的编码数据逐位分配到每个具有x = [（K-1） ）/（mn）]串联移位级。 这里，[p]表示实数p以上的最小整数。 n个模2加法电路与所有移位寄存器的所有移位级的连接由定义n个解码生成多项式的n个解码生成向量定义。 模2加法电路对与其连接的移位级的输出执行模2加法，并输出n个加法结果作为n位的解码结果。 从解码N行的生成矢量中选出n个解码生成矢量，该矢量作为其矩阵的逆矩阵而获得，该矩阵的元素是定义N = m×卷积码生成多项式的N×N个系数。

    Digital communication system using superposed transmission of high speed and low speed digital signals
    9.
    发明授权
    Digital communication system using superposed transmission of high speed and low speed digital signals 失效
    数字通信系统采用叠加传输的高速和低速数字信号

    公开(公告)号：US5280537A

    公开(公告)日：1994-01-18

    申请号：US980919

    申请日：1992-11-24

    申请人： Takatoshi Sugiyama ,  Shuji Kubota ,  Masahiro Morikura ,  Kiyoshi Enomoto ,  Shuzo Kato

    发明人： Takatoshi Sugiyama ,  Shuji Kubota ,  Masahiro Morikura ,  Kiyoshi Enomoto ,  Shuzo Kato

    IPC分类号： H04J13/00 ,  H04B1/707 ,  H04B7/216 ,  H04J99/00 ,  H04N7/20 ,  H04N21/2365 ,  H04N21/647 ,  H04L27/30 ,  H04L5/12 ,  H04J3/22

    CPC分类号： H04B7/216

    摘要： A digital communication system using superposed transmission of high and low speed digital signals capable of transmitting superposed high and low speed digital signals through an identical frequency band efficiently by increasing a simultaneously transmittable number of channels in the low speed digital signals, while achieving the practically reasonable bit error rate performances for both the high speed digital signals and the low speed digital signals. In this system, the low speed digital signals are transmitted in a form of spread spectrum signals and the high speed digital signals are cancelled out from the superposed transmission signals in obtaining the output low speed digital signals by using the phase inverted replica of the high speed digital signals to be combined with the superposed transmission signals, so that it becomes possible to increase a number of channels for the low speed digital signals, while achieving the practically reasonable bit error rate performances for both the high speed digital signals and the low speed digital signals.

    摘要翻译： 一种使用高低速数字信号的叠加传输的数字通信系统，其能够通过在低速数字信号中增加同时可传送的信道数而有效地通过相同频带发送叠加的高速和低速数字信号，同时实现实际合理的 高速数字信号和低速数字信号的误码率性能。 在该系统中，以扩展频谱信号的形式传输低速数字信号，并且通过使用高速的相位反转副本从叠加的发送信号中抵消高速数字信号，从而获得输出的低速数字信号 数字信号与叠加的发送信号组合，使得可以增加用于低速数字信号的通道数，同时实现高速数字信号和低速数字信号的实际合理的比特误码率性能 信号。