公开(公告)号：US09396974B2

公开(公告)日：2016-07-19

申请号：US13245375

申请日：2011-09-26

申请人： Hiroaki Takahashi ,  Toru Endo ,  Masahiro Miyagi ,  Koji Hashimoto

发明人： Hiroaki Takahashi ,  Toru Endo ,  Masahiro Miyagi ,  Koji Hashimoto

IPC分类号： H01L21/67 ,  H01L21/02 ,  G11B7/26 ,  G11B5/84 ,  B05D1/00 ,  H01L21/687

CPC分类号： H01L21/67051 ,  B05D1/005 ,  G11B5/8404 ,  G11B7/266 ,  H01L21/02052 ,  H01L21/68728

摘要： A substrate processing apparatus includes a substrate holding unit that horizontally holds a substrate in non-contact with a major surface of the substrate, a processing liquid supply unit that supplies a processing liquid to the major surface of the substrate held by the substrate holding unit, and a hydrophilic surface placing unit that places an annular hydrophilic surface along a peripheral portion of the major surface of the substrate held by the substrate holding unit such that the hydrophilic surface comes into contact with a liquid film of the processing liquid held on the major surface of the substrate.

摘要翻译： 一种基板处理装置，包括：基板保持单元，其水平地保持与基板的主表面不接触的基板;处理液供给单元，其将处理液供给到由所述基板保持单元保持的基板的主表面; 以及亲水性表面放置单元，其沿着由基板保持单元保持的基板的主表面的周边部分设置环状亲水性表面，使得亲水表面与保持在主表面上的处理液体的液膜接触 的基底。

公开(公告)号：US08883030B2

公开(公告)日：2014-11-11

申请号：US13596903

申请日：2012-08-28

申请人： Masahiro Miyagi ,  Koji Hashimoto ,  Toru Endo

发明人： Masahiro Miyagi ,  Koji Hashimoto ,  Toru Endo

IPC分类号： B44C1/22 ,  B05B1/00 ,  B05D1/02 ,  H01L21/67 ,  B05C13/00 ,  B05C11/10

CPC分类号： B05C11/08 ,  B05B1/00 ,  B05C5/0225 ,  B05C11/10 ,  B05C11/1036 ,  B05C11/1039 ,  B05C13/00 ,  B05D1/02 ,  H01L21/67051

摘要： A substrate processing apparatus comprising a substrate holding rotating mechanism, a process liquid supply mechanism having a nozzle for dispensing a process liquid toward a principal face of the substrate, a processing liquid reservoir for holding sufficient process liquid to form a liquid film covering the whole principal face of the substrate, a liquid film forming unit for forming the liquid film by supplying the process liquid onto the principal face of the substrate in a single burst, and a control unit for controlling the liquid film forming unit and the process liquid supply mechanism such that the process liquid is dispensed from the process liquid nozzle toward the principal face of the substrate after formation of the liquid film covering the whole area of the principal face of the substrate by the liquid film forming unit.

摘要翻译： 一种基板处理装置，包括基板保持旋转机构，具有用于向基板的主面分配处理液的喷嘴的处理液供给机构，用于保持足够的处理液以形成覆盖整个主体的液膜的处理液储存器 基板的表面，用于通过将处理液体单次供给到基板的主面上来形成液膜的液膜形成单元，以及用于控制液膜形成单元和处理液供给机构的控制单元， 在通过液膜形成单元形成覆盖基板的主面的整个区域的液膜之后，处理液体从处理液喷嘴分配到基板的主面。

公开(公告)号：US08395504B2

公开(公告)日：2013-03-12

申请号：US12227285

申请日：2007-05-16

申请人： Kozue Furuichi ,  Toru Endo ,  Manabu Suzuki ,  Hidehiko Kando

发明人： Kozue Furuichi ,  Toru Endo ,  Manabu Suzuki ,  Hidehiko Kando

IPC分类号： G08B13/14

CPC分类号： G06K19/07381 ,  G06K19/0776 ,  G06K19/07798

摘要： An IC label for prevention of forgery includes: a label substrate which has an adhesive agent for affixing the same to an object; a non-contact IC medium which is provided on the label substrate and has an IC chip for storing predetermined identification information and an antenna for wireless transmission of the identification information; and a security function portion which is provided on the label substrate and prevents replication.

摘要翻译： 用于防止伪造的IC标签包括：标签基板，其具有用于将其粘贴到物体上的粘合剂; 设置在标签基板上并具有用于存储预定识别信息的IC芯片和用于识别信息的无线传输的天线的非接触IC介质; 以及设置在标签基板上并防止复制的安全功能部分。

公开(公告)号：US07012829B2

公开(公告)日：2006-03-14

申请号：US11050781

申请日：2005-02-07

申请人： Shoichiro Kawashima ,  Toru Endo ,  Tomohisa Hirayama

发明人： Shoichiro Kawashima ,  Toru Endo ,  Tomohisa Hirayama

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A bit line is connected, via a first pMOS transistor, to a first node whose potential is set at a prescribed negative voltage in advance. The gate voltage of the first pMOS transistor is set at a constant voltage that is slightly lower than its threshold voltage. During a read operation, a current that flows into the bit line from a memory cell in accordance with a residual dielectric polarization value of a ferroelectric capacitor always leaks to the first node, whereby the potential of the first node increases. The logical value of data stored in the memory cell is judged on the basis of a voltage increase at the first node. Since no control circuit for keeping the potential of the first node at the ground potential during a read operation is necessary, the layout size and the power consumption of a ferroelectric memory can be decreased.

摘要翻译： 位线通过第一pMOS晶体管被连接到预先设定为规定负电压的第一节点。 第一pMOS晶体管的栅极电压被设置为略低于其阈值电压的恒定电压。 在读取操作期间，根据铁电电容器的残留介电极化值从存储器单元流入位线的电流总是泄漏到第一节点，从而第一节点的电位增加。 基于第一节点处的电压增加来判断存储在存储单元中的数据的逻辑值。 由于在读取操作期间不需要用于将第一节点的电位保持在地电位的控制电路，因此可以减小铁电存储器的布局尺寸和功耗。

公开(公告)号：US06487130B2

公开(公告)日：2002-11-26

申请号：US09885928

申请日：2001-06-22

申请人： Toru Endo ,  Shoichiro Kawashima

发明人： Toru Endo ,  Shoichiro Kawashima

IPC分类号： G11C1122

CPC分类号： G11C5/147 ,  G11C7/14 ,  G11C11/22

摘要： A semiconductor device includes memory cells of one-transistor one-capacitor connected to n+1 bit lines that are simultaneously driven, sense amplifiers connected to the n+1 bit lines, and a reference voltage generating circuit generates an average voltage of a highest voltage and a lowest voltage among bit line voltages that are obtained by accessing the n+1 bit lines in parallel, and supplying the average voltage to the sense amplifiers as a reference voltage.

公开(公告)号：US06687151B2

公开(公告)日：2004-02-03

申请号：US10308073

申请日：2002-12-03

申请人： Toru Endo ,  Shoichiro Kawashima

发明人： Toru Endo ,  Shoichiro Kawashima

IPC分类号： G11C1100

CPC分类号： G05F1/618

摘要： An output node NO is, on one hand, connected through a PMOS transistor TP1 and an NMOS transistor TN1 to ground, and on the other hand, connected through a PMOS transistor TP2 and an NMOS transistor TN2 to a node N6 which is selectively set to ground and VDD. The output node NO is connected through a capacitor C1 to the input of a driving inverter 11 in order to step-up or step-down the voltage of the output node NO. When the output node NO is set to −1V, the control circuit 10 turns off the PMOS transistors TP1 and TP2. It is also allowed to connect the output node through a first PMOS transistor to a second PMOS transistor whose back gate is connected to a power supply voltage VDD, and to connect the back gate of the first PMOS transistor to one end of a current path thereof on the side of the second PMOS transistor.

摘要翻译： 一方面，输出节点NO通过PMOS晶体管TP1和NMOS晶体管TN1连接到地，另一方面通过PMOS晶体管TP2和NMOS晶体管TN2连接到节点N6，节点N6选择性地被设置为 接地和VDD。 输出节点NO通过电容器C1连接到驱动逆变器11的输入端，以便升压或降压输出节点NO的电压。 当输出节点NO设定为-1V时，控制电路10关断PMOS晶体管TP1和TP2。 也可以将输出节点通过第一PMOS晶体管连接到第二PMOS晶体管，第二PMOS晶体管的背栅极连接到电源电压VDD，并将第一PMOS晶体管的背栅极连接到其电流通路的一端 在第二PMOS晶体管的一侧。

公开(公告)号：US20090303044A1

公开(公告)日：2009-12-10

申请号：US12227285

申请日：2007-05-16

申请人： Kozue Furuichi ,  Toru Endo ,  Manabu Suzuki ,  Hidehiko Kando

发明人： Kozue Furuichi ,  Toru Endo ,  Manabu Suzuki ,  Hidehiko Kando

IPC分类号： G08B21/00 ,  G06K19/06

CPC分类号： G06K19/07381 ,  G06K19/0776 ,  G06K19/07798

摘要： An IC label for prevention of forgery includes: a label substrate which has an adhesive agent for affixing the same to an object; a non-contact IC medium which is provided on the label substrate and has an IC chip for storing predetermined identification information and an antenna for wireless transmission of the identification information; and a security function portion which is provided on the label substrate and prevents replication.

摘要翻译： 用于防止伪造的IC标签包括：标签基板，其具有用于将其粘贴到物体上的粘合剂; 设置在标签基板上并具有用于存储预定识别信息的IC芯片和用于识别信息的无线传输的天线的非接触IC介质; 以及设置在标签基板上并防止复制的安全功能部分。

公开(公告)号：US20050162942A1

公开(公告)日：2005-07-28

申请号：US10829960

申请日：2004-04-23

申请人： Toru Endo

发明人： Toru Endo

IPC分类号： G11C7/06 ,  G11C7/14 ,  G11C11/22 ,  G11C5/00

CPC分类号： G11C7/06 ,  G11C7/14 ,  G11C11/22

摘要： A semiconductor memory device includes a first reference circuit which generates a first reference potential, a second reference circuit which generates a second reference potential, a memory cell, a first sense amplifier which senses a data potential read from the memory cell through comparison with the first reference potential, and a second sense amplifier which senses the data potential read from the memory cell through comparison with the second reference potential, wherein the first sense amplifier and the second sense amplifier cooperate to determine whether the data potential is “0” or “1”, the first reference potential being positioned on a highest potential side of a data potential distribution of a “0” data potential read from the memory cell, and the second reference potential being positioned on a lowest potential side of a data potential distribution of a “1” data potential read from the memory cell.

摘要翻译： 半导体存储器件包括产生第一参考电位的第一参考电路，产生第二参考电位的第二参考电路，存储单元，第一读出放大器，其通过与第一参考电位的比较来检测从存储单元读取的数据电位 以及第二读出放大器，其通过与第二参考电位比较来感测从存储单元读取的数据电位，其中第一读出放大器和第二读出放大器协作确定数据电位是“0”还是“1” “，第一参考电位位于从存储单元读取的”0“数据电位的数据电位分布的最高电位侧，并且第二参考电位位于数据电位分布的最低电位侧 从存储单元读取“1”数据电位。

公开(公告)号：US06538915B2

公开(公告)日：2003-03-25

申请号：US10272998

申请日：2002-10-18

申请人： Toru Endo ,  Shoichiro Kawashima

发明人： Toru Endo ,  Shoichiro Kawashima

IPC分类号： G11C1122

CPC分类号： G11C5/147 ,  G11C7/14 ,  G11C11/22

摘要： A semiconductor device includes memory cells of one-transistor one-capacitor connected to n+1 bit lines that are simultaneously driven, sense amplifiers connected to the n+1 bit lines, and a reference voltage generating circuit generates an average voltage of a highest voltage and a lowest voltage among bit line voltages that are obtained by accessing the n+1 bit lines in parallel, and supplying the average voltage to the sense amplifiers as a reference voltage.

公开(公告)号：US06434051B1

公开(公告)日：2002-08-13

申请号：US09926648

申请日：2001-11-28

申请人： Toru Endo

发明人： Toru Endo

IPC分类号： G11C1606

CPC分类号： G11C16/28 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0441 ,  G11C27/005

摘要： The present invention provides a non-volatile memory circuit that can easily read and write. Especially, the present invention is effective to storage multi-value or analog value. The present invention has a storage transistor Nc with a floating gate and a feedback transistor Nf with a floating gate whose source are connected commonly and a load circuit is provided to the drain side of both transistors. A negative feedback circuit is provided between the drain of the storage transistor Nc and the floating gate of the feedback transistor Nf. An output transistor P2 is a preferable example of the negative feedback circuit, whose gate is connected to the drain of the storage transistor and which generates a voltage corresponding to that gate voltage at an output terminal. This output terminal and the floating gate of the feedback transistor are connected. A memory circuit of such a configuration operates so that the voltage corresponding to the charge in the floating gate of the storage transistor Nc and the output voltage of the output terminal OUT become the same. Therefore, the voltage of the floating gate of the storage transistor can be directly detected.

摘要翻译： 本发明提供一种易于读写的非易失性存储器电路。 特别地，本发明对存储多值或模拟值是有效的。 本发明具有具有浮动栅极的存储晶体管Nc和具有浮动栅极的反馈晶体管Nf，其源极共同连接，并且负载电路被提供给两个晶体管的漏极侧。 在存储晶体管Nc的漏极和反馈晶体管Nf的浮置栅极之间提供负反馈电路。 输出晶体管P2是负反馈电路的优选实例，其栅极连接到存储晶体管的漏极，并且在输出端产生对应于该栅极电压的电压。 该输出端子和反馈晶体管的浮栅连接。 这种结构的存储电路工作，使得与存储晶体管Nc的浮置栅极中的电荷相对应的电压和输出端子OUT的输出电压变得相同。 因此，可以直接检测存储晶体管的浮置栅极的电压。