公开(公告)号：US20110316049A1

公开(公告)日：2011-12-29

申请号：US13254638

申请日：2009-03-02

申请人： Masahiro Sugimoto ,  Narumasa Soejima ,  Tsutomu Uesugi ,  Masahito Kodama ,  Eiko Ishii

发明人： Masahiro Sugimoto ,  Narumasa Soejima ,  Tsutomu Uesugi ,  Masahito Kodama ,  Eiko Ishii

IPC分类号： H01L29/778 ,  H01L21/20

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66462 ,  H01L29/7788

摘要： Provided are a vertical nitride semiconductor device in which occurrence of leak currents can be suppressed, and a method for manufacturing such nitride semiconductor device. A nitride semiconductor device, which is a vertical HEMT, is provided with an n− type GaN first nitride semiconductor layer, p+ type GaN second nitride semiconductor layers, an n− type GaN third nitride semiconductor layer, and an n− type AlGaN fourth nitride semiconductor layer that is in hetero junction with a front surface of the third nitride semiconductor layer. Openings that penetrate the third nitride semiconductor layer and reach front surfaces of the second nitride semiconductor layers are provided at positions isolated from the peripheral edge of the third nitride semiconductor layer. Source electrodes are provided in the openings. Etching damage that is in contact with the source electrodes is surrounded by a region where no etching damage is formed.

摘要翻译： 提供了可以抑制泄漏电流的发生的垂直氮化物半导体器件，以及这种氮化物半导体器件的制造方法。 作为垂直HEMT的氮化物半导体器件设置有n型GaN第一氮化物半导体层，p +型GaN第二氮化物半导体层，n型GaN第三氮化物半导体层和n型AlGaN第四氮化物半导体层 半导体层，其与第三氮化物半导体层的前表面处于异质结。 穿过第三氮化物半导体层并到达第二氮化物半导体层的前表面的开口设置在与第三氮化物半导体层的外围边缘隔离的位置处。 源电极设置在开口中。 与源电极接触的蚀刻损伤被没有形成蚀刻损伤的区域包围。

公开(公告)号：US5708286A

公开(公告)日：1998-01-13

申请号：US623702

申请日：1996-03-29

申请人： Tsutomu Uesugi ,  Masahito Kodama

发明人： Tsutomu Uesugi ,  Masahito Kodama

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/66666 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/66484 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7831

摘要： A vertical semiconductor device having an insulated gate structure makes use of a double-gate structure. The double-gate structure dramatically reduces the channel resistance, JFET resistance, and epitaxial resistance of the on-resistance of the power MOSFET, and implements an adequate breakdown voltage due to the effect of gate bias. In principle, a first gate and second gate having mutually facing portions are driven synchronously. This causes first and second channels to be formed in correspondence with first and second gates, and the currents flowing through these first and second channels form the on-current for this power device having a vertical structure.

摘要翻译： 具有绝缘栅极结构的垂直半导体器件采用双栅结构。 双栅极结构显着降低了功率MOSFET导通电阻的沟道电阻，JFET电阻和外延电阻，并由于栅极偏置的影响而实现了足够的击穿电压。 原则上，具有相互面对部分的第一栅极和第二栅极被同步地驱动。 这使得与第一和第二栅极对应地形成第一和第二通道，并且流过这些第一和第二通道的电流形成具有垂直结构的该功率器件的导通电流。

公开(公告)号：US06700175B1

公开(公告)日：2004-03-02

申请号：US10019567

申请日：2001-12-31

申请人： Masahito Kodama ,  Tsutomu Uesugi

发明人： Masahito Kodama ,  Tsutomu Uesugi

IPC分类号： H01L2358

CPC分类号： H01L29/7802 ,  H01L21/2255 ,  H01L21/2257 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/4236 ,  H01L29/66712 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a method of manufacturing a vertical semiconductor device including a structural section in which an n−-type semiconductor region and a p−-type semiconductor region are arranged alternately without filling trenches by epitaxial growth. A p−-type silicon layer (13) which becomes a p−-type semiconductor region (12) is formed. An n−-type semiconductor region (11) is formed by diffusing n-type impurities into the p−-type silicon layer (13) through the sidewalls of first trenches (22) formed in the p−-type silicon layer (13).

摘要翻译： 提供一种制造垂直半导体器件的方法，其包括结构部分，其中n +型半导体区域和p - 型半导体区域交替布置，而不通过外延生长填充沟槽。 形成成为p型半导体区域（12）的p +型硅层（13）。 n型半导体区域（11）通过将n型杂质扩散通过形成在p型衬底（13）中的第一沟槽（22）的侧壁而扩散到p型硅层（13）中而形成， 型硅层（13）。

公开(公告)号：US6072215A

公开(公告)日：2000-06-06

申请号：US275868

申请日：1999-03-25

申请人： Sachiko Kawaji ,  Masahito Kodama ,  Takashi Suzuki ,  Tsutomu Uesugi

发明人： Sachiko Kawaji ,  Masahito Kodama ,  Takashi Suzuki ,  Tsutomu Uesugi

IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L31/113

CPC分类号： H01L29/66704 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/66325 ,  H01L29/66674 ,  H01L29/7393 ,  H01L29/7394 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7831

摘要： Disclosed is a semiconductor device including a lateral MOS element which comprises a p-type silicon substrate; a first semiconductor layer of an n-type constituting a drift region; a second semiconductor layer of the p-type selectively provided in the first semiconductor layer, and constituting a body region, in which a channel region is partially formed; a third semiconductor layer of the n-type selectively provided in a surface of the second semiconductor layer, and constituting a source region; a fourth semiconductor layer of the n-type provided in the first semiconductor layer, and constituting a drain region; and a trench gate. The trench gate is constructed such that a trench formed in the first semiconductor layer is filled with a gate electrode with an insulating film interposed therebetween. The trench gate is formed such that at least a bottom thereof is in contact with the semiconductor substrate. The semiconductor device of the present invention prevents a high electric field at a corner of the bottom of the trench gate, thus achieving its high breakdown voltage.

摘要翻译： 公开了包括p型硅衬底的横向MOS元件的半导体器件; 构成漂移区域的n型的第一半导体层; p型的第二半导体层选择性地设置在第一半导体层中，并且构成其中部分地形成沟道区的体区; n型的第三半导体层选择性地设置在第二半导体层的表面中，并构成源极区; n型的第四半导体层，设置在第一半导体层中，构成漏区; 和一个沟槽门。 沟槽栅被构造成使得形成在第一半导体层中的沟槽填充有绝缘膜插入其间的栅电极。 沟槽栅极形成为至少其底部与半导体衬底接触。 本发明的半导体器件防止沟槽栅极底部拐角处的高电场，从而实现其高击穿电压。

公开(公告)号：US07696071B2

公开(公告)日：2010-04-13

申请号：US11976450

申请日：2007-10-24

申请人： Masahito Kodama ,  Eiko Hayashi ,  Masahiro Sugimoto

发明人： Masahito Kodama ,  Eiko Hayashi ,  Masahiro Sugimoto

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/02433 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265

摘要： The invention provides a method for producing a group III nitride based semiconductor having a reduced number of crystal defects.A GaN layer 2 is epitaxially grown on a sapphire substrate 1 having C-plane as a main plane (FIG. 1A). Then, the layer is wet-etched by use of a 25% aqueous TMAH solution at 85° C. for one hour, to thereby form an etch pit 4 (FIG. 1B). Then, a GaN layer 5 is grown on the GaN layer 2 through the ELO method (FIG. 1C). The thus-formed GaN layer 5 has a screw dislocation density lower than that of the GaN layer 2.

摘要翻译： 本发明提供一种具有减少晶体缺陷数的III族氮化物基半导体的制造方法。 在具有C面作为主平面的蓝宝石衬底1上外延生长GaN层2（图1A）。 然后，使用25％TMAH水溶液在85℃湿法蚀刻该层1小时，从而形成蚀刻坑4（图1B）。 然后，通过ELO方法在GaN层2上生长GaN层5（图1C）。 如此形成的GaN层5的螺旋位错密度低于GaN层2的位错密度。

公开(公告)号：US06844246B2

公开(公告)日：2005-01-18

申请号：US10472261

申请日：2002-03-19

申请人： Seiji Nagai ,  Kazuyoshi Tomita ,  Masahito Kodama

发明人： Seiji Nagai ,  Kazuyoshi Tomita ,  Masahito Kodama

IPC分类号： H01L21/20 ,  H01L21/205 ,  H01L33/32 ,  H01S5/323 ,  H01S5/343

CPC分类号： H01L33/007 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647

摘要： A GaN layer 32 grows in vertical direction on a GaN layer 31 where neither a first mask 41m nor a second mask 42m is formed. When thickness of the GaN layer 32 becomes larger than that of the first mask 41m, it began to grown in lateral direction so as to cover the first mask 41m. Because the second mask 42m is not formed on the upper portion of the first mask 41m, the GaN layer 32 grows in vertical direction. On the contrary, at the upper region of the GaN layer 31 where the mask 41m is not formed, the second mask 42m is formed like eaves, the growth of the GaN layer 32 stops and threading dislocations propagated with vertical growth also stops there. The GaN layer 32 grows in vertical direction so as to penetrate the region where neither the first mask 41m nor the second mask 42m is formed. When the height of the GaN layer 32 becomes larger than that of the second mask 42m, the GaN layer 32 begins to grow in lateral direction again and covers the second mask 42m. After the GaN layer 32 completely covers the second mask 42m, it began to grow in vertical direction.

摘要翻译： GaN层32在不形成第一掩模41m和第二掩模42m的GaN层31上沿垂直方向生长。 当GaN层32的厚度大于第一掩模41m的厚度时，它开始在横向上生长以覆盖第一掩模41m。 因为第二掩模42m未形成在第一掩模41m的上部，所以GaN层32在垂直方向上生长。 相反，在未形成掩模41m的GaN层31的上部区域，第二掩模42m形成为像屋檐，GaN层32的生长停止，并且随着垂直生长而传播的穿透位错也停止。 GaN层32在垂直方向上生长，从而穿过第一掩模41m和第二掩模42m都不形成的区域。 当GaN层32的高度变得大于第二掩模42m的高度时，GaN层32再次在横向方向上开始覆盖第二掩模42m。 在GaN层32完全覆盖第二掩模42m之后，它开始在垂直方向上生长。