公开(公告)号：US20090152623A1

公开(公告)日：2009-06-18

申请号：US12335701

申请日：2008-12-16

申请人： Masakazu GOTO ,  Nobutoshi AOKI ,  Takashi IZUMIDA ,  Kimitoshi OKANO ,  Satoshi INABA ,  Ichiro MIZUSHIMA

发明人： Masakazu GOTO ,  Nobutoshi AOKI ,  Takashi IZUMIDA ,  Kimitoshi OKANO ,  Satoshi INABA ,  Ichiro MIZUSHIMA

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L29/7845

摘要： A fin transistor includes: a substrate; a plurality of semiconductor fins formed on the substrate; a gate electrode covering a channel region of the semiconductor fins; and a member as a stress source for the semiconductor fins included in a region of the gate electrode and the region provided between the semiconductor fins, and the member being made of a different material from the gate electrode.

摘要翻译： 翅片晶体管包括：衬底; 形成在所述基板上的多个半导体翅片; 覆盖半导体鳍片的沟道区域的栅电极; 以及作为用于包括在栅极电极的区域中的半导体鳍片的应力源的构件和设置在半导体鳍片之间的区域，并且该构件由与栅电极不同的材料制成。

公开(公告)号：US20090065869A1

公开(公告)日：2009-03-12

申请号：US12207121

申请日：2008-09-09

申请人： Tatsuya OHGURO ,  Takashi IZUMIDA ,  Satoshi INABA ,  Kimitoshi OKANO ,  Nobutoshi AOKI

发明人： Tatsuya OHGURO ,  Takashi IZUMIDA ,  Satoshi INABA ,  Kimitoshi OKANO ,  Nobutoshi AOKI

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A semiconductor device has a plurality of fins formed on a semiconductor substrate to be separated from each other, a first contact region which connects commonly one end side of the plurality of fins, a second contact region which connects commonly the other end side of the plurality of fins, a gate electrode arranged to be opposed to at least both side surfaces of the plurality of fins by sandwiching a gate insulating film therebetween, a source electrode including the first contact region and the plurality of fins on a side closer to the first contact region than the gate electrode, and a drain electrode including the second contact region and the plurality of fins on a side closer to the second contact than the gate electrode. The ratio Rd/Rs of a resistance Rd of each fin in the drain region to a resistance Rs of each fin in the source region is larger than 1.

摘要翻译： 半导体器件具有形成在半导体衬底上的多个翅片以彼此分离，第一接触区域与多个翅片的共同的一端侧连接;第二接触区域，其共同连接多个翅片的另一端侧; 翅片，栅电极，通过在其间夹有栅极绝缘膜而布置成与所述多个翅片的至少两个侧表面相对，在所述第一触点更靠近所述第一触点的一侧包括所述第一接触区域和所述多个翅片的源电极 区域，以及包括第二接触区域的漏电极和在比栅电极更靠近第二接触的一侧的多个翅片。 漏极区域中的每个鳍​​片的电阻Rd与源极区域中的每个鳍​​片的电阻Rs的比Rd / Rs大于1。

公开(公告)号：US20110121381A1

公开(公告)日：2011-05-26

申请号：US12719193

申请日：2010-03-08

申请人： Takahisa KANEMURA ,  Tomomi KUSAKA ,  Takashi IZUMIDA ,  Masaki KONDO ,  Nobutoshi AOKI

发明人： Takahisa KANEMURA ,  Tomomi KUSAKA ,  Takashi IZUMIDA ,  Masaki KONDO ,  Nobutoshi AOKI

IPC分类号： H01L29/788

CPC分类号： H01L29/7883 ,  G11C16/0441 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324

摘要： A semiconductor memory device according to an embodiment of the present invention includes a substrate, a first gate insulator formed on the substrate and serving as an F-N (Fowler-Nordheim) tunneling film, a first floating gate formed on the first gate insulator, a second gate insulator formed on the first floating gate and serving as an F-N tunneling film, a second floating gate formed on the second gate insulator, an intergate insulator formed on the second floating gate and serving as a charge blocking film, and a control gate formed on the intergate insulator, at least one of the first and second floating gates including a metal layer.

摘要翻译： 根据本发明的实施例的半导体存储器件包括：衬底，形成在衬底上并用作FN（Fowler-Nordheim）隧穿膜的第一栅极绝缘体，形成在第一栅极绝缘体上的第一浮动栅极，第二栅极绝缘体 形成在第一浮栅上并用作FN隧道膜的栅极绝缘体，形成在第二栅极绝缘体上的第二浮栅，形成在第二浮栅上并用作电荷阻挡膜的栅极绝缘体，以及形成在栅极绝缘体上的控制栅极 所述隔间绝缘体，所述第一和第二浮动栅极中的至少一个包括金属层。

公开(公告)号：US20120139031A1

公开(公告)日：2012-06-07

申请号：US13364602

申请日：2012-02-02

申请人： Takashi IZUMIDA ,  Nobutoshi AOKI

发明人： Takashi IZUMIDA ,  Nobutoshi AOKI

IPC分类号： H01L27/088

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/0688 ,  H01L27/11578 ,  H01L27/11582

摘要： In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insulating layer and a first gate electrode respectively, and the select transistor is at least composed of a second insulating layer and a second gate electrode. The first gate electrode is provided with a first silicide layer of a first width formed on the first insulating layer. The second gate electrode is provided with an impurity-doped silicon layer formed on the second insulating layer and with a second silicide layer of a second width formed on the impurity-doped silicon layer. The second silicide has the same composition as the first silicide. The second width is larger than the first width.

公开(公告)号：US20130240970A1

公开(公告)日：2013-09-19

申请号：US13602634

申请日：2012-09-04

申请人： Masaki KONDO ,  Nobutoshi AOKI ,  Takashi IZUMIDA ,  Tomomi YODA

发明人： Masaki KONDO ,  Nobutoshi AOKI ,  Takashi IZUMIDA ,  Tomomi YODA

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L29/788 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/7883

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a floating gate electrode formed on the gate insulating film, made of polysilicon containing a p-type impurity as a group XIII element, and having a lower film and an upper film stacked on the lower film, an inter-electrode insulating film formed on the floating gate electrode, and a control gate electrode formed on the inter-electrode insulating film. One of a concentration and an activation concentration of the p-type impurity in the upper film is higher than one of a concentration and an activation concentration of the p-type impurity in the lower film.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括半导体衬底，形成在半导体衬底上的栅绝缘膜，形成在栅极绝缘膜上的浮栅，由含有p型杂质的多晶硅组成， 并且具有层叠在下膜上的下膜和上膜，形成在浮栅上的电极间绝缘膜和形成在电极间绝缘膜上的控制栅电极。 上膜中的p型杂质的浓度和活化浓度之一高于下膜中的p型杂质的浓度和活化浓度之一。

公开(公告)号：US20130069148A1

公开(公告)日：2013-03-21

申请号：US13601400

申请日：2012-08-31

申请人： Takashi IZUMIDA ,  Nobutoshi AOKI

发明人： Takashi IZUMIDA ,  Nobutoshi AOKI

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/4983 ,  H01L21/28061 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66621

摘要： According to one embodiment, a semiconductor device includes an element region partitioned by an isolation region in a semiconductor substrate, and a source region and a drain region formed in a surface layer of the element region by being isolated by a gate trench along a predetermined direction across the element region. The semiconductor device includes a gate electrode formed to reach a position deeper than the source region and the drain region by embedding at least part thereof in the gate trench with a gate dielectric film interposed therebetween. An interface in the drain region, which is in contact with the gate dielectric film, includes a projection projecting toward the gate electrode side.

摘要翻译： 根据一个实施例，半导体器件包括由半导体衬底中的隔离区分隔开的元件区域，以及通过沿预定方向的栅极沟槽隔离形成在元件区域的表面层中的源极区域和漏极区域 跨越元素区域。 半导体器件包括通过在栅极沟槽中至少部分地嵌入栅极电介质膜而形成为达到比源极区域和漏极区域更深的位置的栅电极。 与栅极电介质膜接触的漏极区域中的界面包括向栅电极侧突出的突起。

公开(公告)号：US20110122698A1

公开(公告)日：2011-05-26

申请号：US12719420

申请日：2010-03-08

申请人： Takashi IZUMIDA ,  Tomomi Kusaka ,  Masaki Kondo ,  Nobutoshi Aoki

发明人： Takashi IZUMIDA ,  Tomomi Kusaka ,  Masaki Kondo ,  Nobutoshi Aoki

IPC分类号： G11C16/04 ,  H01L29/792

CPC分类号： H01L29/7881 ,  G11C16/0408 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11531 ,  H01L29/42332 ,  H01L29/7887

摘要： A semiconductor memory device according to an embodiment of the present invention includes a substrate, a gate insulator formed on the substrate and serving as an F-N (Fowler-Nordheim) tunneling film, a first floating gate formed on the gate insulator, a first intergate insulator formed on the first floating gate and serving as an F-N tunneling film, a second floating gate formed on the first intergate insulator, a second intergate insulator formed on the second floating gate and serving as a charge blocking film, and a control gate formed on the second intergate insulator.

摘要翻译： 根据本发明的实施例的半导体存储器件包括：衬底，形成在衬底上并用作FN（Fowler-Nordheim）隧穿膜的栅极绝缘体，形成在栅极绝缘体上的第一浮栅，第一栅极绝缘体 形成在第一浮栅上并用作FN隧道膜，形成在第一栅极绝缘体上的第二浮栅，形成在第二浮栅上并用作电荷阻挡膜的第二栅极绝缘体，以及形成在第一浮栅上的控制栅 第二隔间绝缘子。

公开(公告)号：US20090289293A1

公开(公告)日：2009-11-26

申请号：US12470030

申请日：2009-05-21

申请人： Takashi IZUMIDA ,  Takahisa Kanemura ,  Nobutoshi Aoki

发明人： Takashi IZUMIDA ,  Takahisa Kanemura ,  Nobutoshi Aoki

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A semiconductor device of an example of the invention comprises a memory cell and a select gate transistor provided for the memory cell. A gate electrode of the select gate transistor has a Tri-gate structure in which an upper surface of a gate insulating film formed above a channel of the select gate transistor is set higher than a portion of an upper surface of an element isolation region of the select gate transistor.

摘要翻译： 本发明实施例的半导体器件包括为存储单元提供的存储单元和选择栅极晶体管。 选择栅极晶体管的栅电极具有三栅结构，其中形成在选择栅极晶体管的沟道上方的栅极绝缘膜的上表面被设定为高于栅极绝缘膜的元件隔离区的上表面的一部分 选择栅极晶体管。

公开(公告)号：US20090267155A1

公开(公告)日：2009-10-29

申请号：US12402093

申请日：2009-03-11

申请人： Takashi IZUMIDA ,  Nobutoshi AOKI

发明人： Takashi IZUMIDA ,  Nobutoshi AOKI

IPC分类号： H01L29/165 ,  H01L21/04

CPC分类号： H01L29/7851 ,  H01L29/1054 ,  H01L29/66795

摘要： A semiconductor device has a semiconductor substrate, a semiconductor fin which is formed on the semiconductor substrate, which has a long side direction and a short side direction, and which has a carbon-containing silicon film including an impurity and a silicon film formed on the carbon-containing silicon film, a gate electrode which is formed to face both side surfaces of the semiconductor fin in the short side direction, source and drain regions which are respectively formed in the semiconductor fin located in the direction of both sides in the long side direction of the semiconductor fin so as to sandwich the gate electrode, and an element isolation insulating film which is formed on the side surface of the semiconductor fin and between the gate electrode and the semiconductor substrate.

摘要翻译： 半导体器件具有半导体衬底，形成在半导体衬底上的具有长边方向和短边方向的半导体鳍片，并且具有包含杂质的含碳硅膜和形成在其上的硅膜 含碳硅膜，形成为在短边方向上面对半导体翅片的两侧面的栅电极，分别形成在长边方向两侧的半导体翅片中的源区和漏区 半导体鳍片的方向以夹着栅极电极;以及元件隔离绝缘膜，其形成在半导体鳍片的侧表面上以及栅电极和半导体衬底之间。

公开(公告)号：US20080251854A1

公开(公告)日：2008-10-16

申请号：US12100621

申请日：2008-04-10

申请人： Yoshiaki SHIMOOKA ,  Takashi IZUMIDA ,  Hiroki OKAMOTO

发明人： Yoshiaki SHIMOOKA ,  Takashi IZUMIDA ,  Hiroki OKAMOTO

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L27/092 ,  H01L29/7843 ,  H01L29/7846

摘要： In one aspect of the present invention, semiconductor device, may include a p-channel semiconductor active region, an n-channel semiconductor active region, an element isolation insulating layer which electrically isolates the p-channel semiconductor active region from the n-channel semiconductor active region, and an insulating layer made of a material different from that of the element isolation insulating layer, and being in contact with both ends, in its channel length direction, of the p-channel semiconductor active region to apply a compression stress in the channel length direction to a channel of the p-channel semiconductor active region, wherein the p-channel semiconductor active region is surrounded by the insulating layer, which is in contact with the both ends, in the channel length direction, of the p-channel semiconductor active region, and the p-channel semiconductor active region is surrounded by the element isolation insulating layer, which is in contact with the side surfaces, approximately parallel to the channel length direction, of the p-channel semiconductor active region, and the n-channel semiconductor active region is surrounded by the element isolation insulating layer.

摘要翻译： 在本发明的一个方面，半导体器件可以包括p沟道半导体有源区，n沟道半导体有源区，将p沟道半导体有源区与n沟道半导体电隔离的元件隔离绝缘层 有源区，以及由与元件隔离绝缘层不同的材料制成的绝缘层，并且在其沟道长度方向上与p沟道半导体有源区的两端接触，以在该沟道长度方向上施加压缩应力 沟道长度方向到p沟道半导体有源区的沟道，其中p沟道半导体有源区被p沟道的沟道长度方向上与两端接触的绝缘层包围 半导体有源区和p沟道半导体有源区被与侧面接触的元件隔离绝缘层包围 大致平行于沟道长度方向的表面，并且n沟道半导体有源区被元件隔离绝缘层包围。