公开(公告)号：US07662685B2

公开(公告)日：2010-02-16

申请号：US11234217

申请日：2005-09-26

申请人： Masamichi Suzuki ,  Takeshi Yamaguchi

发明人： Masamichi Suzuki ,  Takeshi Yamaguchi

IPC分类号： H01L21/8242

CPC分类号： H01L21/02175 ,  C23C14/08 ,  C23C14/28 ,  H01L21/28194 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： A semiconductor device includes a Si substrate, a gate insulating film formed on the Si substrate, the gate insulating film being formed of an oxide film containing at least one selected from the group of Zr, Hf, Ti and a lanthanoid series metal, and having a single local minimal value on a high binding energy side of an inflection point in first differentiation of an O1s photoelectron spectrum, and a gate electrode formed on the gate insulating film.

摘要翻译： 半导体器件包括Si衬底，形成在Si衬底上的栅极绝缘膜，所述栅极绝缘膜由包含选自Zr，Hf，Ti和镧系元素金属中的至少一种的氧化物膜形成，并且具有 在O1s光电子光谱的第一微分中的拐点的高结合能量侧的单个局部最小值，以及形成在栅极绝缘膜上的栅电极。

公开(公告)号：US20080318404A1

公开(公告)日：2008-12-25

申请号：US12149572

申请日：2008-05-05

申请人： Masamichi Suzuki ,  Daisuke Matsushita ,  Takeshi Yamaguchi

发明人： Masamichi Suzuki ,  Daisuke Matsushita ,  Takeshi Yamaguchi

IPC分类号： H01L21/28

CPC分类号： H01L29/517 ,  H01L21/2807 ,  H01L21/28194 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/513

摘要： A semiconductor device includes a silicon substrate; an insulation layer formed on the silicon substrate, the insulation layer containing an oxide of an element of at least one kind selected from at least Hf, Zr, Ti and Ta; an electrode formed on the insulation layer; and a metal oxide layer containing La and Al, the metal oxide layer being provided at at least one of an interface between the silicon substrate and the insulation layer and an interface between the insulation layer and the electrode.

摘要翻译： 半导体器件包括硅衬底; 形成在所述硅基板上的绝缘层，所述绝缘层含有至少一种选自Hf，Zr，Ti和Ta中的至少一种元素的氧化物; 形成在所述绝缘层上的电极; 以及包含La和Al的金属氧化物层，所述金属氧化物层设置在所述硅衬底和所述绝缘层之间的界面中的至少一个以及所述绝缘层和所述电极之间的界面。

公开(公告)号：US07833865B2

公开(公告)日：2010-11-16

申请号：US12149572

申请日：2008-05-05

申请人： Masamichi Suzuki ,  Daisuke Matsushita ,  Takeshi Yamaguchi

发明人： Masamichi Suzuki ,  Daisuke Matsushita ,  Takeshi Yamaguchi

IPC分类号： H01L29/788

CPC分类号： H01L29/517 ,  H01L21/2807 ,  H01L21/28194 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/513

摘要： A semiconductor device includes a silicon substrate; an insulation layer formed on the silicon substrate, the insulation layer containing an oxide of an element of at least one kind selected from at least Hf, Zr, Ti and Ta; an electrode formed on the insulation layer; and a metal oxide layer containing La and Al, the metal oxide layer being provided at at least one of an interface between the silicon substrate and the insulation layer and an interface between the insulation layer and the electrode.

摘要翻译： 半导体器件包括硅衬底; 形成在所述硅基板上的绝缘层，所述绝缘层含有至少一种选自Hf，Zr，Ti和Ta中的至少一种元素的氧化物; 形成在所述绝缘层上的电极; 以及包含La和Al的金属氧化物层，所述金属氧化物层设置在所述硅衬底和所述绝缘层之间的界面中的至少一个以及所述绝缘层和所述电极之间的界面。

公开(公告)号：US20060086993A1

公开(公告)日：2006-04-27

申请号：US11234217

申请日：2005-09-26

申请人： Masamichi Suzuki ,  Takeshi Yamaguchi

发明人： Masamichi Suzuki ,  Takeshi Yamaguchi

IPC分类号： H01L29/94 ,  H01L29/788

CPC分类号： H01L21/02175 ,  C23C14/08 ,  C23C14/28 ,  H01L21/28194 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： A semiconductor device includes a Si substrate, a gate insulating film formed on the Si substrate, the gate insulating film being formed of an oxide film containing at least one selected from the group of Zr, Hf, Ti and a lanthanoid series metal, and having a single local minimal value on a high binding energy side of an inflection point in first differentiation of an O1s photoelectron spectrum, and a gate electrode formed on the gate insulating film.

摘要翻译： 半导体器件包括Si衬底，形成在Si衬底上的栅极绝缘膜，所述栅极绝缘膜由包含选自Zr，Hf，Ti和镧系元素金属中的至少一种的氧化物膜形成，并且具有 在O1s光电子光谱的第一微分中的拐点的高结合能量侧的单个局部最小值，以及形成在栅极绝缘膜上的栅电极。

公开(公告)号：US20060054961A1

公开(公告)日：2006-03-16

申请号：US11176271

申请日：2005-07-08

申请人： Masamichi Suzuki ,  Daisuke Matsushita ,  Takeshi Yamaguchi

发明人： Masamichi Suzuki ,  Daisuke Matsushita ,  Takeshi Yamaguchi

IPC分类号： H01L29/94

CPC分类号： H01L29/517 ,  H01L21/2807 ,  H01L21/28194 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/513

摘要： A semiconductor device includes a silicon substrate; an insulation layer formed on the silicon substrate, the insulation layer containing an oxide of an element of at least one kind selected from at least Hf, Zr, Ti and Ta; an electrode formed on the insulation layer; and a metal oxide layer containing La and Al, the metal oxide layer being provided at at least one of an interface between the silicon substrate and the insulation layer and an interface between the insulation layer and the electrode.

摘要翻译： 半导体器件包括硅衬底; 形成在所述硅基板上的绝缘层，所述绝缘层含有至少一种选自Hf，Zr，Ti和Ta中的至少一种元素的氧化物; 形成在所述绝缘层上的电极; 以及包含La和Al的金属氧化物层，所述金属氧化物层设置在所述硅衬底和所述绝缘层之间的界面中的至少一个以及所述绝缘层和所述电极之间的界面。

公开(公告)号：US09246709B2

公开(公告)日：2016-01-26

申请号：US13293399

申请日：2011-11-10

申请人： Kosuke Tatsumura ,  Atsuhiro Kinoshita ,  Hirotaka Nishino ,  Masamichi Suzuki ,  Yoshifumi Nishi ,  Takao Marukame ,  Takahiro Kurita

发明人： Kosuke Tatsumura ,  Atsuhiro Kinoshita ,  Hirotaka Nishino ,  Masamichi Suzuki ,  Yoshifumi Nishi ,  Takao Marukame ,  Takahiro Kurita

IPC分类号： G06F12/02 ,  H04L12/64 ,  G06F3/06

CPC分类号： H04L49/253 ,  G06F3/0605 ,  G06F3/0635 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0683 ,  H04L12/6418 ,  H04L45/74

摘要： According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.

摘要翻译： 根据一个实施例，存储设备包括多个存储器节点。 每个存储器节点包括多个输入端口，多个输出端口，选择器，分组控制器和存储器。 选择器将输入到输入端口的数据包输出输出到其中一个输出端口。 分组控制器控制选择器。 内存存储数据。 存储器节点在输入端口和输出端口相互连接。 存储器节点具有由其物理位置确定的地址。 当接收到没有寻址到具有分组控制器的存储器节点的分组时，分组控制器基于包括分组的目的地地址的信息和具有分组控制器的存储器节点的地址来切换输出分组的输出端口 。

公开(公告)号：US20130076551A1

公开(公告)日：2013-03-28

申请号：US13535118

申请日：2012-06-27

申请人： Takao MARUKAME ,  Tetsufumi Tanamoto ,  Atsuhiro Kinoshita ,  Tomoaki Inokuchi ,  Masamichi Suzuki ,  Yoshiaki Saito

发明人： Takao MARUKAME ,  Tetsufumi Tanamoto ,  Atsuhiro Kinoshita ,  Tomoaki Inokuchi ,  Masamichi Suzuki ,  Yoshiaki Saito

IPC分类号： H03M1/36

CPC分类号： H03M1/1061 ,  H03F3/45183 ,  H03F2203/45391 ,  H03F2203/45392 ,  H03F2203/45674 ,  H03K5/2481 ,  H03M1/365

摘要： According to an embodiment, an analog-to-digital converter includes a voltage generating unit to generate comparative voltages; and comparators. Each comparator compares any one of the comparative voltages with an analog input voltage and output a digital signal. Each comparator includes a differential pair circuit to detect a potential difference between two inputs. The differential pair circuit includes first and second circuit portions. The first circuit portion includes a first transistor having a gate to which one input is supplied; and a resistor connected in series with the first transistor. The second circuit portion includes a second transistor having a gate to which the other input is supplied and forms a differential pair with the first transistor; and a variable resistor connected in series with the second transistor. The variable resistor includes variable resistive elements each having a resistance value variably set according to a control signal.

摘要翻译： 根据实施例，模数转换器包括产生比较电压的电压产生单元; 和比较者。 每个比较器将比较电压中的任何一个与模拟输入电压进行比较，并输出数字信号。 每个比较器包括用于检测两个输入之间的电位差的差分对电路。 差分对电路包括第一和第二电路部分。 第一电路部分包括具有一个输入端的栅极的第一晶体管; 以及与第一晶体管串联连接的电阻器。 第二电路部分包括第二晶体管，其具有提供另一输入的栅极，并与第一晶体管形成差分对; 以及与第二晶体管串联连接的可变电阻器。 可变电阻器包括可变电阻元件，每个电阻元件具有根据控制信号可变地设置的电阻值。

公开(公告)号：US07755089B2

公开(公告)日：2010-07-13

申请号：US11858408

申请日：2007-09-20

申请人： Masamichi Suzuki ,  Masato Koyama

发明人： Masamichi Suzuki ,  Masato Koyama

IPC分类号： H01L31/112

CPC分类号： H01L21/823807 ,  H01L21/28079 ,  H01L21/28097 ,  H01L21/28194 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/47 ,  H01L29/4958 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7845

摘要： A semiconductor device includes a semiconductor substrate, p-type first and n-type second semiconductor regions formed on the substrate so as to be insulated with each other, n-channel and p-channel MOS transistors formed on the first and second semiconductor regions, the n-channel transistor including a first pair of source/drain regions formed on the first semiconductor region, a first gate insulator formed in direct contact with the first semiconductor region and formed as an amorphous insulator containing at least La, and a first gate electrode formed on the first gate insulator, the p-channel MOS transistor including a second pair of source/drain regions formed opposite to each other on the second semiconductor region, a second gate insulator including a silicon oxide film and the amorphous insulating film formed thereon on the second semiconductor region, and a second gate electrode formed on the second gate insulator.

摘要翻译： 半导体器件包括半导体衬底，形成在衬底上以彼此绝缘的p型第一和n型第二半导体区，形成在第一和第二半导体区上的n沟道和p沟道MOS晶体管， 所述n沟道晶体管包括形成在所述第一半导体区域上的第一对源极/漏极区域，与所述第一半导体区域直接接触形成并形成为至少包含La的非晶绝缘体的第一栅极绝缘体和第一栅极电极 形成在所述第一栅极绝缘体上的所述p沟道MOS晶体管，包括在所述第二半导体区域上彼此相对形成的第二对源极/漏极区域，包括氧化硅膜的第二栅极绝缘体和在其上形成的非晶绝缘膜 第二半导体区域和形成在第二栅极绝缘体上的第二栅电极。

公开(公告)号：US07421594B2

公开(公告)日：2008-09-02

申请号：US11023298

申请日：2004-12-27

申请人： Kenji Nakajima ,  Kazuhide Ooba ,  Masamichi Suzuki

发明人： Kenji Nakajima ,  Kazuhide Ooba ,  Masamichi Suzuki

IPC分类号： G06F1/00

CPC分类号： G06F1/266

摘要： A bus power device includes a connector that is connected to a port of a host apparatus compliant with a predetermined interface standard; a current/voltage detecting unit that detects a current/voltage supplied from the host apparatus to a bus power line via the port and the connector; and a power assisting unit that assists a current to the bus power line based on a result of comparison between the current detected by the current/voltage detecting unit and a threshold current, and assists a voltage to the bus power line by an amount of shortfalls in the voltage based on a result of comparison between the voltage detected by the current/voltage detecting unit and a threshold voltage.

摘要翻译： 总线功率器件包括连接到符合预定接口标准的主设备的端口的连接器; 电流/电压检测单元，其经由端口和连接器检测从主机设备提供给总线电力线的电流/电压; 以及功率辅助单元，其基于由电流/电压检测单元检测到的电流与阈值电流之间的比较结果，辅助电流到总线电力线，并且辅助总线电力线的电压减少量 基于由电流/电压检测单元检测的电压与阈值电压之间的比较结果的电压。

公开(公告)号：US07348644B2

公开(公告)日：2008-03-25

申请号：US11407077

申请日：2006-04-20

申请人： Masahiro Koike ,  Masato Koyama ,  Tsunehiro Ino ,  Yuuichi Kamimuta ,  Akira Takashima ,  Masamichi Suzuki ,  Akira Nishiyama

发明人： Masahiro Koike ,  Masato Koyama ,  Tsunehiro Ino ,  Yuuichi Kamimuta ,  Akira Takashima ,  Masamichi Suzuki ,  Akira Nishiyama

IPC分类号： H01L29/94

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/517 ,  H01L29/518

摘要： Disclosed is a semiconductor device comprising a substrate, an insulating film formed above the substrate and containing a metal, Si, N and O, the insulating film containing metal-N bonds larger than the sum total of metal-metal bonds and metal-Si bonds, and an electrode formed above the insulating film.

摘要翻译： 公开了一种半导体器件，其包括基板，形成在基板上方并且包含金属Si，N和O的绝缘膜，所述绝缘膜含有大于金属 - 金属键和金属-Si键的总和的金属-N键 ，以及形成在绝缘膜上方的电极。