公开(公告)号：US5021357A

公开(公告)日：1991-06-04

申请号：US561424

申请日：1990-08-01

申请人： Masao Taguchi ,  Taiji Ema

发明人： Masao Taguchi ,  Taiji Ema

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/92

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/40 ,  H01L28/87

摘要： A dynamic random access memory device includes a storage capacitor having a plurality of stacked conductive films which form a storage electrode. A gap is formed between elevationally adjacent conductive films so as to surround the storage electrode. A gap is also formed between an insulating film which covers a gate electrode for insulation and a lowermost film of the storage electrode. Connection between the adjacent films may be established so that an uppermost film elevationally extends so as to make contact with a drain region. Also, connection can be established so that an upper film is mounted directly on an lower film. An end portion of the film may be thicker than the other portion thereof. The stacked film structure may be produced by alternatively forming a film made of a material different from the insulating film covering the gate electrode, and a conductive film.

公开(公告)号：US5175128A

公开(公告)日：1992-12-29

申请号：US789192

申请日：1991-11-08

申请人： Taiji Ema ,  Hisatsugu Shirai ,  Katsuyoshi Kobayashi ,  Masao Taguchi

发明人： Taiji Ema ,  Hisatsugu Shirai ,  Katsuyoshi Kobayashi ,  Masao Taguchi

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/027 ,  H01L21/30 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L28/87 ,  H01L21/0274 ,  H01L21/76802 ,  Y10S438/946

摘要： A method for fabricating a semiconductor device comprises the steps of defining a plurality of regions on a substrate, exposing a first pattern that extends over a plurality of such regions such that the first pattern is exposed on the plurality of regions simultaneously, and exposing a plurality of second patterns that are identical in size and shape and isolated from each other, consecutively for each of the plurality of regions.

公开(公告)号：US5071783A

公开(公告)日：1991-12-10

申请号：US376470

申请日：1989-07-05

申请人： Masao Taguchi ,  Taiji Ema

发明人： Masao Taguchi ,  Taiji Ema

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/87

摘要： A dynamic random access memory device includes a storage capacitor having a plurality of stacked conductive films which form a storage electrode. A gap is formed between elevationally adjacent conductive films so as to surround the storage electrode. A gap is also formed between an insulating film which covers a gate electrode for insulation and a lowermost film of the storage electrode. Connection between the adjacent films may be established so that an uppermost film elevationally extends so as to make contact with a drain region. Also, connection can be established so that an upper film is mounted directly on a lower film. An end portion of the film may be thicker than the other portion thereof. The stacked film structure may be produced by alternatively forming a film made of a material different from the insulating film covering the gate electrode, and a conductive film.

摘要翻译： 动态随机存取存储器件包括具有形成存储电极的多个层叠导电膜的存储电容器。 在垂直相邻的导电膜之间形成间隙以包围存储电极。 在覆盖用于绝缘的栅电极的绝缘膜和存储电极的最下面的膜之间也形成间隙。 可以建立相邻膜之间的连接，使得最上面的膜垂直地延伸以与漏区接触。 此外，可以建立连接，使得上部膜直接安装在下部膜上。 膜的端部可以比其它部分厚。 层叠膜结构可以通过交替地形成由与覆盖栅电极的绝缘膜不同的材料制成的膜和导电膜来制造。

公开(公告)号：US5650647A

公开(公告)日：1997-07-22

申请号：US329056

申请日：1994-10-26

申请人： Masao Taguchi ,  Taiji Ema

发明人： Masao Taguchi ,  Taiji Ema

IPC分类号： H01L21/02 ,  H01L29/68 ,  H01L29/78

CPC分类号： H01L28/87

摘要： A dynamic random access memory device includes a storage capacitor having a plurality of stacked conductive films which form a storage electrode. A gap is formed between elevationally adjacent conductive films so as to surround the storage electrode. A gap is also formed between an insulating film which covers a gate electrode for insulation and a lowermost film of the storage electrode. Connection between the adjacent films may be established so that an uppermost film elevationally extends so as to make contact with a drain region. Also, connection can be established so that an upper film is mounted directly on an lower film. An end portion of the film may be thicker than the other portion thereof. The stacked film structure may be produced by alternatively forming a film made of a material different from the insulating film covering the gate electrode, and a conductive film.

摘要翻译： 动态随机存取存储器件包括具有形成存储电极的多个层叠导电膜的存储电容器。 在垂直相邻的导电膜之间形成间隙以包围存储电极。 在覆盖用于绝缘的栅电极的绝缘膜和存储电极的最下面的膜之间也形成间隙。 可以建立相邻膜之间的连接，使得最上面的膜垂直地延伸以与漏区接触。 此外，可以建立连接，使得上部膜直接安装在下部膜上。 膜的端部可以比其它部分厚。 层叠膜结构可以通过交替地形成由与覆盖栅电极的绝缘膜不同的材料制成的膜和导电膜来制造。

公开(公告)号：US4974040A

公开(公告)日：1990-11-27

申请号：US496107

申请日：1990-03-16

申请人： Masao Taguchi ,  Taiji Ema

发明人： Masao Taguchi ,  Taiji Ema

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/92

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/40 ,  H01L28/87

摘要： A dynamic random access memory device includes a storage capacitor having a plurality of stacked conductive films which form a storage electrode. A gap is formed between elevationally adjacent conductive films so as to surround the storage electrode. A gap is also formed between an insulating film which covers a gate electrode for insulation and a lowermost film of the storage electrode. Connection between the adjacent films may be established so that an uppermost film elevationally extends so as to make contact with a drain region. Also, connection can be established so that an upper film is mounted directly on a lower film. An end portion of the film may be thicker than the other portion thereof. The stacked film structure may be produced by alternatively forming a film made of a material different from the insulating film covering the gate electrode, and a conductive film.

公开(公告)号：US08921981B2

公开(公告)日：2014-12-30

申请号：US13618389

申请日：2012-09-14

申请人： Kazutaka Yoshizawa ,  Taiji Ema ,  Takuya Moriki

发明人： Kazutaka Yoshizawa ,  Taiji Ema ,  Takuya Moriki

IPC分类号： H01L23/544 ,  H01L21/78 ,  H01L21/66

摘要： A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.

公开(公告)号：US08530308B2

公开(公告)日：2013-09-10

申请号：US12651058

申请日：2009-12-31

申请人： Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki

发明人： Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki

IPC分类号： H01L21/336 ,  H01L29/66

CPC分类号： H01L27/11526 ,  H01L21/76237 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/105 ,  H01L27/11546

摘要： An integrated circuit device comprises a memory cell well formed with a flash memory device, first and second well of opposite conductivity types for formation of high voltage transistors, and third and fourth wells of opposite conductivity types for low voltage transistors, wherein at least one of the first and second wells and at least one of the third and fourth wells have an impurity distribution profile steeper than the memory cell well.

摘要翻译： 一种集成电路器件包括一个形成有闪存器件的存储器单元，用于形成高压晶体管的相反导电类型的第一和第二阱以及用于低压晶体管的相反导电类型的第三和第四阱，其中至少一个 第一阱和第二阱以及第三阱和第四阱中的至少一个具有比存储单元阱更陡的杂质分布分布。

公开(公告)号：US08283729B2

公开(公告)日：2012-10-09

申请号：US13010255

申请日：2011-01-20

申请人： Tomohiko Tsutsumi ,  Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki

发明人： Tomohiko Tsutsumi ,  Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki

IPC分类号： H01L23/62

CPC分类号： H01L27/0629 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/0266 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546

摘要： The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.

摘要翻译： 半导体器件包括第一MIS晶体管，其包括栅极绝缘膜92，形成在栅极绝缘膜92和源极/漏极区154上的栅电极108，包括比栅极绝缘膜92厚的栅极绝缘膜96的第二MIS晶体管 形成在栅极绝缘膜96上的栅极电极108，源极/漏极区域154以及连接到源极/漏极区域154之一的镇流电阻器120，在具有绝缘膜的镇流电阻器120上形成的自对准硅绝缘膜146 92，比其间的栅极绝缘膜96薄，以及形成在源极/漏极区154上的硅化物膜156。

公开(公告)号：US20100283092A1

公开(公告)日：2010-11-11

申请号：US12839867

申请日：2010-07-20

申请人： Taiji Ema ,  Tohru Anezaki

发明人： Taiji Ema ,  Tohru Anezaki

IPC分类号： H01L27/108

CPC分类号： H01L27/10852 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897

摘要： The semiconductor device includes a first conductor formed over a semiconductor substrate; a first insulator formed over the first conductor; a second insulator formed over the first insulator, the second insulator having an etching characteristic different from an etching characteristic of the first insulator; a second conductor formed on the second insulator, the second conductor being in contact with the second insulator; a third insulator formed over the second conductor, the third insulator having an etching characteristic different from the etching characteristic of the second insulator; a first contact hole formed through the third insulator and the second conductor, the first contact hole reaching the second insulator; a third conductor formed in the first contact hole, wherein a side wall of the third conductor is electrically connected to a side wall of the second conductor; a second contact hole formed through the third insulator and the first insulator, the second contact hole reaching the first conductor; and a fourth conductor formed in the second contact hole, wherein the fourth conductor is electrically connected to the first conductor.

摘要翻译： 半导体器件包括形成在半导体衬底上的第一导体; 形成在所述第一导体上的第一绝缘体; 形成在所述第一绝缘体上的第二绝缘体，所述第二绝缘体具有与所述第一绝缘体的蚀刻特性不同的蚀刻特性; 形成在所述第二绝缘体上的第二导体，所述第二导体与所述第二绝缘体接触; 形成在所述第二导体上的第三绝缘体，所述第三绝缘体具有与所述第二绝缘体的蚀刻特性不同的蚀刻特性; 通过第三绝缘体和第二导体形成的第一接触孔，第一接触孔到达第二绝缘体; 形成在第一接触孔中的第三导体，其中第三导体的侧壁电连接到第二导体的侧壁; 形成为穿过所述第三绝缘体和所述第一绝缘体的第二接触孔，所述第二接触孔到达所述第一导体; 以及形成在所述第二接触孔中的第四导体，其中所述第四导体电连接到所述第一导体。

公开(公告)号：US20100238716A1

公开(公告)日：2010-09-23

申请号：US12792115

申请日：2010-06-02

申请人： Toru Anezaki ,  Tomohiko Tsutsumi ,  Tatsuji Araya ,  Hideyuki Kojima ,  Taiji Ema

发明人： Toru Anezaki ,  Tomohiko Tsutsumi ,  Tatsuji Araya ,  Hideyuki Kojima ,  Taiji Ema

IPC分类号： G11C11/00 ,  G11C11/34

CPC分类号： H01L27/1104 ,  G11C5/063 ,  G11C11/412 ,  H01L27/11 ,  Y10S257/903

摘要： A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.

摘要翻译： 半导体器件包括第一CMOS反相器，第二CMOS反相器，第一传输晶体管和第二传输晶体管，其中第一和第二传输晶体管分别形成在由器件隔离区限定在半导体器件上的第一和第二器件区域中， 为了彼此并联延伸，第一传输晶体管在第一器件区域上的第一位接触区域处与第一位线接触，第二传输晶体管在第二位线处与第二位线接触，第二位线在第二位接触区域处 器件区域，其中第一位接触区域形成在第一器件区域中，使得所述位接触区域的中心朝向第二器件区域偏移，并且其中第二位接触区域形成在第二器件区域中，使得 第二位接触区域的中心朝向第一器件区域偏移。