公开(公告)号：US20050049809A1

公开(公告)日：2005-03-03

申请号：US10915345

申请日：2004-08-11

申请人： Shiro Dosho ,  Naoshi Yanagisawa ,  Masaomi Toyama ,  Keijiro Umehara

发明人： Shiro Dosho ,  Naoshi Yanagisawa ,  Masaomi Toyama ,  Keijiro Umehara

IPC分类号： G01R31/316 ,  G01R35/00 ,  G06F19/00

CPC分类号： G01R35/005 ,  G01R31/316

摘要： An analog circuit automatic calibration system for calibrating an object circuit that is an analog circuit having a characteristic changing with an input set value. The system includes: a set value storage section for storing a value and outputting the value to the object circuit as the set value; a characteristic detection section for detecting the characteristic of the object circuit; a first characteristic change section for determining the set value so that the characteristic of the object circuit is optimized; a second characteristic change section for updating the set value so that the characteristic of the object circuit is maintained, using an algorithm different from that used in the first characteristic change section; and a selector for selecting either one of the outputs of the first and second characteristic sections to enable the selected one to be stored in the set value storage section.

摘要翻译： 一种模拟电路自动校准系统，用于校准作为具有随着输入设定值变化的特性的模拟电路的目标电路。 该系统包括：设定值存储部分，用于存储值并将该值输出到对象电路作为设定值; 用于检测所述目标电路的特性的特性检测部分; 用于确定所述设定值使得所述对象电路的特性被优化的第一特征变化部分; 第二特征变化部，使用与第一特征变化部中使用的算法不同的算法来更新设定值，使得保持对象电路的特性; 以及选择器，用于选择第一和第二特征部分的输出之一，以使所选择的一个存储在设定值存储部分中。

公开(公告)号：US06982581B2

公开(公告)日：2006-01-03

申请号：US10713162

申请日：2003-11-17

申请人： Shiro Dosho ,  Naoshi Yanagisawa ,  Masaomi Toyama ,  Keijiro Umehara

发明人： Shiro Dosho ,  Naoshi Yanagisawa ,  Masaomi Toyama ,  Keijiro Umehara

IPC分类号： H03K3/017

CPC分类号： H03K5/133 ,  H03K5/1565

摘要： In order to correct the duty cycle of a given clock signal to produce a clock signal with a 50% duty cycle, a duty cycle correction circuit includes a delay unit for delaying a first clock signal to output a second clock signal and a clock-signal output unit. The clock-signal output unit includes two transistors which use the first and second clock signals as the inputs of respective gates and an inverter circuit for inverting a signal output from a common drain of the transistors to output a third clock signal. The delay unit delays the first clock signal so that the first clock signal falling appears at a timing at which the duty cycle thereof becomes 50%. The two transistors in the clock-signal output unit output, as the third clock signal, a ground voltage and a source voltage as the signal from the common drain in response to the rising of the first clock signal and the falling of the second clock signal, respectively.

摘要翻译： 为了校正给定时钟信号的占空比以产生具有50％占空比的时钟信号，占空比校正电路包括用于延迟第一时钟信号以输出第二时钟信号和时钟信号的延迟单元 输出单元。 时钟信号输出单元包括使用第一和第二时钟信号作为各个门的输入的两个晶体管，以及用于反相从晶体管的公共漏极输出的信号以输出第三时钟信号的反相器电路。 延迟单元延迟第一时钟信号，使得第一时钟信号在占空比变为50％的定时出现。 时钟信号输出单元中的两个晶体管响应于第一时钟信号的上升和第二时钟信号的下降而输出作为第三时钟信号的接地电压和源极电压作为来自公共漏极的信号 ， 分别。

公开(公告)号：US20050077955A1

公开(公告)日：2005-04-14

申请号：US10500875

申请日：2003-05-22

申请人： Shiro Dosho ,  Naoshi Yanagisawa ,  Masaomi Toyama ,  Keijiro Umehara ,  Masahiro Fukui ,  Takefumi Yoshikawa ,  Toru Iwata ,  Shiro Sakiyama ,  Ryoichi Suzuki

发明人： Shiro Dosho ,  Naoshi Yanagisawa ,  Masaomi Toyama ,  Keijiro Umehara ,  Masahiro Fukui ,  Takefumi Yoshikawa ,  Toru Iwata ,  Shiro Sakiyama ,  Ryoichi Suzuki

IPC分类号： H03H11/12 ,  H03H11/04 ,  H03L7/08 ,  H03L7/081 ,  H03L7/089 ,  H03L7/093 ,  H03L7/107 ,  H03B1/00

CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L7/0893 ,  H03L7/0896 ,  H03L7/093

摘要： The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.

摘要翻译： 本发明提供一种适合用作PLL或DLL的环路滤波器的低通滤波器，其具有与常规滤波特性相同的滤波特性，并且可以在较小的电路面积中实现。 低通滤波器包括第一滤波装置（31），用于接收输入到低通滤波器的输入信号作为输入，并输出第一电压; 包括在第一过滤装置（31）中的用于允许第一电流根据第一电压流动的电路元件（311） 电流产生装置（32），用于以给定的速率产生与第一电流的第二电流; 第二滤波装置（33），用于接受第二电流作为输入并输出第二电压; 以及添加装置（34），用于将第一电压和第二电压相加，并输出低通滤波器的输出信号，其中第二电流被设置为小于第一电流。

公开(公告)号：US06603219B2

公开(公告)日：2003-08-05

申请号：US09801472

申请日：2001-03-08

申请人： Masaomi Toyama ,  Shiro Dosho ,  Naoshi Yanagisawa

发明人： Masaomi Toyama ,  Shiro Dosho ,  Naoshi Yanagisawa

IPC分类号： H02J100

CPC分类号： H03K17/005 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2224/49175 ,  H01L2924/14 ,  H03K3/03 ,  H03K17/693 ,  Y10T307/391 ,  Y10T307/461 ,  Y10T307/492 ,  H01L2924/00

摘要： A semiconductor integrated circuit includes a plurality of units. Each of the units includes a power supply pad, a function circuit, and a power supply control circuit. The plurality of units each have a first state in which the function circuit is in an operating state by the power supply pad being at a prescribed operating potential and a second state in which the function circuit is in a non-operating state by the power supply pad being at a prescribed non-operating potential. The power supply control circuit includes a switching circuit for connecting the power supply pad to the prescribed non-operating potential. The power supply control circuit in each of the plurality of units closes the switching circuit when at least one of the other units is in the first state and opens the switching circuit otherwise.

摘要翻译： 半导体集成电路包括多个单元。 每个单元包括电源焊盘，功能电路和电源控制电路。 所述多个单元各自具有第一状态，其中所述功能电路处于处于规定操作电位的所述功率电路处于工作状态，以及所述功能电路通过所述电源处于非工作状态的第二状态 垫处于规定的非操作电位。 电源控制电路包括用于将电源焊盘连接到规定的非工作电位的开关电路。 当多个单元中的至少一个处于第一状态时，多个单元中的每个单元中的电源控制电路闭合开关电路，否则打开开关电路。

公开(公告)号：US07254507B2

公开(公告)日：2007-08-07

申请号：US10915345

申请日：2004-08-11

申请人： Shiro Dosho ,  Naoshi Yanagisawa ,  Masaomi Toyama ,  Keijiro Umehara

发明人： Shiro Dosho ,  Naoshi Yanagisawa ,  Masaomi Toyama ,  Keijiro Umehara

IPC分类号： G01R35/02

CPC分类号： G01R35/005 ,  G01R31/316

摘要： An analog circuit automatic calibration system for calibrating an object circuit that is an analog circuit having a characteristic changing with an input set value. The system includes: a set value storage section for storing a value and outputting the value to the object circuit as the set value; a characteristic detection section for detecting the characteristic of the object circuit; a first characteristic change section for determining the set value so that the characteristic of the object circuit is optimized; a second characteristic change section for updating the set value so that the characteristic of the object circuit is maintained, using an algorithm different from that used in the first characteristic change section; and a selector for selecting either one of the outputs of the first and second characteristic sections to enable the selected one to be stored in the set value storage section.

摘要翻译： 一种模拟电路自动校准系统，用于校准作为具有随着输入设定值变化的特性的模拟电路的目标电路。 该系统包括：设定值存储部分，用于存储值并将该值输出到对象电路作为设定值; 用于检测所述目标电路的特性的特性检测部分; 用于确定所述设定值使得所述对象电路的特性被优化的第一特征变化部分; 第二特征变化部，使用与第一特征变化部中使用的算法不同的算法来更新设定值，使得保持对象电路的特性; 以及选择器，用于选择第一和第二特征部分的输出之一，以使所选择的一个存储在设定值存储部分中。

公开(公告)号：US07030688B2

公开(公告)日：2006-04-18

申请号：US10500875

申请日：2003-05-22

申请人： Shiro Dosho ,  Naoshi Yanagisawa ,  Masaomi Toyama ,  Keijiro Umehara ,  Masahiro Fukui ,  Takefumi Yoshikawa ,  Toru Iwata ,  Shiro Sakiyama ,  Ryoichi Suzuki

发明人： Shiro Dosho ,  Naoshi Yanagisawa ,  Masaomi Toyama ,  Keijiro Umehara ,  Masahiro Fukui ,  Takefumi Yoshikawa ,  Toru Iwata ,  Shiro Sakiyama ,  Ryoichi Suzuki

IPC分类号： H03K5/00

CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L7/0893 ,  H03L7/0896 ,  H03L7/093

摘要： The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.

摘要翻译： 本发明提供一种适合用作PLL或DLL的环路滤波器的低通滤波器，其具有与常规滤波特性相同的滤波特性，并且可以在较小的电路面积中实现。 低通滤波器包括第一滤波装置（31），用于接收输入到低通滤波器的输入信号作为输入，并输出第一电压; 包括在第一过滤装置（31）中的用于允许第一电流根据第一电压流动的电路元件（311） 电流产生装置（32），用于以给定的速率产生与第一电流的第二电流; 第二滤波装置（33），用于接受第二电流作为输入并输出第二电压; 以及添加装置（34），用于将第一电压和第二电压相加，并输出低通滤波器的输出信号，其中第二电流被设置为小于第一电流。

公开(公告)号：US06407642B2

公开(公告)日：2002-06-18

申请号：US09752525

申请日：2001-01-03

申请人： Shiro Dosho ,  Naoshi Yanagisawa ,  Masaomi Toyama

发明人： Shiro Dosho ,  Naoshi Yanagisawa ,  Masaomi Toyama

IPC分类号： H03L7085

CPC分类号： H03D13/004 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/18

摘要： A three-state phase detector, including two latches and one NAND gate, is provided with two additional latches. To detect a phase difference between first and second input clock signals R and V, the phase detector alternates among three states responsive to a rising edge of the input R or V signal. Each of the two additional latches and an associated latch in the phase detector together constitute one shift register. When the phase detector gets back to its neutral state, the NAND gate generates a reset signal, thereby resetting all of these four latches. Two isolated pulse generators are further provided. Each of the pulse generators makes the pulse width of a frequency difference pulse signal, output from associated one of the additional latches, constant and then outputs the pulse signal with the constant width.

摘要翻译： 包括两个锁存器和一个“与非”门的三态相位检测器具有两个附加锁存器。 为了检测第一和第二输入时钟信号R和V之间的相位差，相位检测器响应于输入R或V信号的上升沿在三个状态之间交替。 两个附加锁存器中的每一个和相位检测器中的相关锁存器一起构成一个移位寄存器。 当相位检测器回到其中性状态时，与非门产生复位信号，从而复位这四个锁存器的全部。 还提供了两个隔离的脉冲发生器。 每个脉冲发生器使得从相关联的一个附加锁存器输出的频差脉冲信号的脉冲宽度恒定，然后输出具有恒定宽度的脉冲信号。

公开(公告)号：US06825712B2

公开(公告)日：2004-11-30

申请号：US10385427

申请日：2003-03-12

申请人： Shiro Dosho ,  Takashi Morie ,  Hitoshi Kobayashi ,  Norihide Kinugasa ,  Masaomi Toyama

发明人： Shiro Dosho ,  Takashi Morie ,  Hitoshi Kobayashi ,  Norihide Kinugasa ,  Masaomi Toyama

IPC分类号： H03K500

CPC分类号： H03H11/04

摘要： In a front end that has a filter circuit and is used for a communication system having an asymmetric communication channel in which upstream and downstream data rates are different, a filter circuit for received signals, which is for filtering received signals, and a filter circuit for transmitted signals, which is for filtering transmitted signals, are provided. The filter circuit for received signals has an amplifier block including a plurality of amplifiers, a capacitor block including a plurality of capacitors and being connected to the plurality of amplifiers included in the amplifier block, and a first and a second resistor blocks each including a plurality of resistors. Either one of the first or the second resistor block is selectively switched so as to be connected to the amplifier block by a resistor block-switching circuit. The circuit scale is reduced since only one amplifier block and one capacitor block are commonly used for two kinds of filter circuits.

摘要翻译： 在具有滤波器电路的前端中，用于具有上行和下行数据速率不同的非对称通信信道的通信系统，用于对接收信号进行滤波的接收信号的滤波电路和用于 提供用于滤波发送信号的发送信号。 用于接收信号的滤波器电路具有包括多个放大器的放大器模块，包括多个电容器并且连接到放大器模块中所包括的多个放大器的电容器模块，以及包括多个放大器的第一和第二电阻块 的电阻。 选择性地切换第一或第二电阻器块中的任何一个，以便通过电阻器块切换电路连接到放大器块。 由于只有一个放大器块和一个电容器块通常用于两种滤波器电路，电路规模减小。

公开(公告)号：US20060038201A1

公开(公告)日：2006-02-23

申请号：US11200060

申请日：2005-08-10

申请人： Noriko Shinomiya ,  Masaomi Toyama ,  Hiroyuki Konishi

发明人： Noriko Shinomiya ,  Masaomi Toyama ,  Hiroyuki Konishi

IPC分类号： H01L27/10

CPC分类号： G06F17/5081

摘要： A layout symmetry constraint checking method and apparatus for efficiently checking a layout symmetry constraint is provided. The layout symmetry constraint is checked by performing a first checking step of checking, for example, a match between shapes of a symmetrical element pair for input layout data, a second checking step of checking whether or not a relative positional relationship between elements is contradictory to the layout symmetry constraint, and a third checking step of checking whether or not a geometric placement of the elements satisfies the layout symmetry constraint. When an error occurs in each of the checking steps, a cause for the error is specified and presented to the designer, thereby achieving efficient layout design.

摘要翻译： 提供了一种用于有效地检查布局对称约束的布局对称约束检查方法和装置。 通过执行第一检查步骤来检查布局对称性约束，例如检查用于输入布局数据的对称元件对的形状之间的匹配，第二检查步骤，用于检查元件之间的相对位置关系是否相矛盾 布局对称性约束，以及检查元素的几何位置是否满足布局对称约束的第三检查步骤。 当在每个检查步骤中发生错误时，指定错误的原因并呈现给设计者，从而实现有效的布局设计。