公开(公告)号：US08742804B2

公开(公告)日：2014-06-03

申请号：US13473658

申请日：2012-05-17

申请人： Masashi Fujita ,  Yukio Maehashi

发明人： Masashi Fujita ,  Yukio Maehashi

IPC分类号： H03B19/06

CPC分类号： H03K3/356156 ,  H03K21/023 ,  H03K23/44 ,  H03K23/52

摘要： A semiconductor device with low power consumption and a small area is provided. By using a transistor including an oxide semiconductor for a channel as a transistor included in a flip-flop circuit, a divider circuit in which the number of transistors is small, power consumption is low, and the area is small can be achieved. By using the divider circuit, a semiconductor device which operates stably and is highly reliable can be provided.

摘要翻译： 提供具有低功耗和小面积的半导体器件。 通过使用包括用于沟道的氧化物半导体的晶体管作为包括在触发器电路中的晶体管，可以实现晶体管数量少，功耗低，面积小的分压电路。 通过使用分压电路，可以提供稳定运转且高可靠性的半导体装置。

公开(公告)号：US5287471A

公开(公告)日：1994-02-15

申请号：US556484

申请日：1990-07-24

申请人： Tsuyoshi Katayose ,  Yukio Maehashi

发明人： Tsuyoshi Katayose ,  Yukio Maehashi

IPC分类号： G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28

摘要： A data transfer controller for controlling DMA data transfer between a memory area and a peripheral unit. The data transfer controller has a first register which stores address information relative to a predetermined address of the memory area. A DMA control unit uses the first register and a second register to perform the DMA data transfer between the memory area and the peripheral unit. The data transfer controller also has a third register for storing data used for accessing the memory area of the DMA transfer. An updater is used to update the contents of the third register whenever a memory access uses the third register and is different from a memory access associated with data transfer between the memory area and the peripheral unit. Finally, a counter changes the contents of the third register in one direction whenever the data transfer between the memory area and the peripheral unit is performed. The counter changes the contents of the third register in an opposite direction whenever memory access using the third register is performed.

摘要翻译： 一种数据传输控制器，用于控制存储区和外设之间的DMA数据传输。 数据传输控制器具有第一寄存器，其存储相对于存储器区域的预定地址的地址信息。 DMA控制单元使用第一寄存器和第二寄存器来执行存储器区域和外围单元之间的DMA数据传输。 数据传输控制器还具有用于存储用于访问DMA传输的存储区域的数据的第三寄存器。 只要存储器访问使用第三寄存器并且与存储器区域和外围单元之间的数据传输相关联的存储器访问不同，更新器被用于更新第三寄存器的内容。 最后，每当执行存储器区域和外围单元之间的数据传输时，计数器在一个方向上改变第三寄存器的内容。 当执行使用第三个寄存器的存储器访问时，计数器以相反的方向改变第三寄存器的内容。

公开(公告)号：US4953082A

公开(公告)日：1990-08-28

申请号：US310577

申请日：1989-02-15

申请人： Masahiro Nomura ,  Yukio Maehashi

发明人： Masahiro Nomura ,  Yukio Maehashi

IPC分类号： G06F15/167 ,  G06F9/38 ,  G06F9/44 ,  G06F15/82

CPC分类号： G06F9/3889 ,  G06F9/3879 ,  G06F9/4436

摘要： An information processing apparatus with a dual processor system contains a general purpose processor for processing a required program and a special purpose processor for processing a specific operation in the required program. The special purpose processor is designed according to a data flow architecture and executes a task according to a token prepared by the general purpose processor, the token having a sequence control information and a data to be processed.

公开(公告)号：US4930068A

公开(公告)日：1990-05-29

申请号：US118671

申请日：1987-11-09

申请人： Tsuyoshi Katayose ,  Yukio Maehashi

发明人： Tsuyoshi Katayose ,  Yukio Maehashi

IPC分类号： G06F13/24

CPC分类号： G06F13/24

摘要： A data processor comprises an interrupt processing request controller receiving processing requests from peripheral devices for generating an interrupt request. An execution unit has a first mode of executing the interrupt processing in accordance with a user's program and a second mode of executing the interrupt processing in accordance with a microprogram while maintaining an internal condition concerning execution of a program. The controller operates to selectively inhibit the execution of the interrupt processing in the first mode, but to basically allow the execution of the interrupt processing in the second mode.

摘要翻译： 数据处理器包括接收来自外围设备的处理请求以产生中断请求的中断处理请求控制器。 执行单元具有根据用户程序执行中断处理的第一模式和根据微程序执行中断处理的第二模式，同时保持关于程序执行的内部条件。 控制器操作以选择性地禁止第一模式中的中断处理的执行，而基本上允许在第二模式中执行中断处理。

公开(公告)号：US4233665A

公开(公告)日：1980-11-11

申请号：US971129

申请日：1978-12-19

申请人： Yukio Maehashi ,  Hidetoshi Kosaka

发明人： Yukio Maehashi ,  Hidetoshi Kosaka

IPC分类号： G06F15/02 ,  G06F3/02 ,  G06F17/00 ,  G06F17/10 ,  G06F15/20

CPC分类号： G06Q10/109

摘要： A date data processor verifies whether an inputted date data exists or not. Inputted date data is stored in an input register which is composed of three sections according to month, day and year. A first calculating unit calculates the days difference between the inputted date data and a reference date, and the results are temporarily stored. A second calculating unit then performs an inverse calculating to arrive at a date based on the previously calculated days difference. The resulting date is compared with the inputted date to complete the verification.

摘要翻译： 日期数据处理器验证输入的日期数据是否存在。 输入日期数据存储在根据月，日，年三个部分组成的输入寄存器中。 第一计算单元计算输入的日期数据和参考日期之间的日期差，并且暂时存储结果。 第二计算单元然后基于先前计算的天差进行逆计算以达到日期。 将结果日期与输入的日期进行比较以完成验证。

公开(公告)号：US4181861A

公开(公告)日：1980-01-01

申请号：US884398

申请日：1978-03-08

申请人： Yukio Maehashi

发明人： Yukio Maehashi

IPC分类号： G06F13/42 ,  G11C19/18 ,  G11C19/28 ,  H03K5/1252 ,  H03K5/135 ,  H03K19/0175 ,  H03K1/10

CPC分类号： G11C19/28 ,  G11C19/184 ,  H03K5/1252 ,  H03K5/135

摘要： A circuit for removing noise from an incoming input signal and for producing a noise free output signal in synchronism with a predetermined synchronization scheme. The memory signal is shifted through a plurality of series connected memory stages in sequence with first and second clock pulse sequences. The output signals of predetermined memory stages are compared and a noise free output signal is produced in response to stage output signals being simultaneously present at the output terminal of predetermined memory stages. The circuit does not utilize capacitors and resistors and is suitable for fabrication as an integrated circuit.

摘要翻译： 一种用于从输入输入信号中去除噪声并与预定同步方案同步产生无噪声输出信号的电路。 存储器信号按照与第一和第二时钟脉冲序列顺序移动通过多个串联连接的存储器级。 比较预定存储器级的输出信号，并响应于同步存在于预定存储级的输出端的级输出信号产生无噪声输出信号。 该电路不使用电容器和电阻器，并且适合作为集成电路制造。

公开(公告)号：US4989223A

公开(公告)日：1991-01-29

申请号：US441112

申请日：1989-11-27

申请人： Tsuyoshi Katayose ,  Yukio Maehashi

发明人： Tsuyoshi Katayose ,  Yukio Maehashi

IPC分类号： H04L7/033

CPC分类号： H04L7/0331

摘要： A serial clock generating circuit for generating a serial clock in phase with a clock included in a received serial data on the basis of an input clock having a frequency N times of a serial data transfer rate of the received serial data, comprises an edge detector for detecting a level transition of the received serial data so as to generate a level transition detection signal, and a counter for counting the input clock. A first comparison register is provided for comparing a count value of the counter with a first programmable predetermined value at each one counting operation of the counter, so as to generate a first coincidence signal when the count value of the counter is coincident with the first programmable predetermined value. A second comparison register is provided for comparing the count value of the counter with a second programmable predetermined value at each one counting operation of the counter, so as to generate a second coincidence signal when the count value of the counter is coincident with the second programmable predetermined value. A capture/comparison register operates to capture and store the count value of the counter when the level transition detection signal is generated, and also to compare the count value of the counter with the stored count value at each one counting operation of the counter, so as to generate a third coincidence signal when the count value of the counter is coincident with the stored count value. There is provided a clear circuit for generating a clear signal to the counter when either the first coincidence signal or the third coincidence signal is generated. A serial clock generator generates a serial clock signal on the basis of the second coincidence signal and the clear signal.

公开(公告)号：US4847867A

公开(公告)日：1989-07-11

申请号：US91803

申请日：1987-09-01

申请人： Masaki Nasu ,  Shigetatsu Katori ,  Yukio Maehashi ,  Kazutoshi Yoshizawa

发明人： Masaki Nasu ,  Shigetatsu Katori ,  Yukio Maehashi ,  Kazutoshi Yoshizawa

IPC分类号： G06F13/40 ,  G06F13/42

CPC分类号： G06F13/4077 ,  G06F13/4256

摘要： A serial data communication system is disclosed. This system includes a plurality of stations which are interconnected by a single clock wire and a single data wire. A master station in the stations includes a transistor push-pull circuit for driving the clock wire to output a clock signal on the clock wire. The clock signal thus has sharp leading and falling edges. The data wire is coupled to wire logic means. A transmitting station transmits each bit of a data signal on the data wire in synchronism with one of leading and falling edges of the associated clock pulse of the clock signal, and a receiving station receives each bit of the data signal in synchronism with the other of leading and falling edges of the associated clock pulse.

摘要翻译： 公开了一种串行数据通信系统。 该系统包括通过单个时钟线和单个数据线互连的多个站。 站中的主站包括用于驱动时钟线的晶体管推挽电路，以在时钟线上输出时钟信号。 因此，时钟信号具有尖锐的引导和下降沿。 数据线耦合到线逻辑装置。 发送站与时钟信号的相关联的时钟脉冲的前沿和下降沿中的一个同步地在数据线上传输数据信号的每一位，并且接收站与另一个的同步接收数据信号的每一位 相关时钟脉冲的前沿和下降沿。

公开(公告)号：US4196362A

公开(公告)日：1980-04-01

申请号：US885219

申请日：1978-03-10

申请人： Yukio Maehashi

发明人： Yukio Maehashi

IPC分类号： G06F1/24 ,  H03K3/356 ,  H03K17/22 ,  H03K5/153

CPC分类号： H03K17/223 ,  H03K3/356008

摘要： A clear signal generating circuit for initializing a logic circuit upon the application of power to the logic circuit. The generator circuit comprises a level detection circuit for generating a detection signal when the power supply voltage reaches or exceeds a predetermined value, a counter circuit which commences to count in response to the detection signal and which generates a trigger pulse upon reaching a predetermined count and a status storage circuit which is placed in a first state in response to the occurrence of the detection signal and placed in a second state in response to the trigger pulse. The output of the status storage circuit is utilized as the generator circuit output.

摘要翻译： 一种用于在向逻辑电路施加电力时初始化逻辑电路的清除信号发生电路。 发电机电路包括电平检测电路，用于当电源电压达到或超过预定值时产生检测信号;计数器电路响应于检测信号开始计数，并在达到预定计数时产生触发脉冲， 状态存储电路，其响应于所述检测信号的发生而处于第一状态，并且响应于所述触发脉冲而处于第二状态。 状态存储电路的输出用作发电机电路输出。

公开(公告)号：US10079053B2

公开(公告)日：2018-09-18

申请号：US13444177

申请日：2012-04-11

申请人： Takuro Ohmaru ,  Yukio Maehashi

发明人： Takuro Ohmaru ,  Yukio Maehashi

IPC分类号： G11C14/00 ,  G11C11/412

CPC分类号： G11C11/412 ,  G11C14/0054

摘要： An object is to provide a memory element having a novel structure where data can be held even after power supply is stopped. The memory element includes a latch circuit, a first selection circuit, a second selection circuit, a first nonvolatile memory circuit, and a second nonvolatile memory circuit. The first nonvolatile memory circuit and the second nonvolatile memory circuit each include a transistor and a capacitor. The transistor included in each of the first nonvolatile memory circuit and the second nonvolatile memory circuit is a transistor in which a channel is formed in an oxide semiconductor film. The off-state current of such a transistor is extremely small. The transistor is turned off after data is input to a node where the transistor and the capacitor are connected to each other, and data can be held for a long time even after supply of power supply voltage is stopped.