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1.发明申请METHOD OF MANUFACTURING INTEGRATED CIRCUITS INCLUDING A FET WITH A GATE SPACER 有权制造集成电路的方法，其中包括具有栅极间隔的FET公开(公告)号：US20100078711A1
公开(公告)日：2010-04-01
申请号：US12242039
申请日：2008-09-30
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides.
摘要翻译： 一种制造集成电路的方法，该集成电路包括具有栅极间隔物的FET。 一个实施例提供了在薄片的相对侧上形成半导体材料的薄片和两个绝缘体结构。 薄片凹进。 翅片由薄片的中心部分形成。 翅片比在翼片的相对侧上彼此面对的薄片的第一和第二部分薄。 形成第一间隔结构，其包围翅片的第一部分，第一部分与第一薄片部分相邻。 栅电极邻近第一间隔结构设置并且在顶侧和两个相对的侧面上包围翅片的另一部分。
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2.发明授权Method of manufacturing integrated circuits including a FET with a gate spacer and a fin 有权制造集成电路的方法，该集成电路包括具有栅极间隔物和鳍的FET公开(公告)号：US07863136B2
公开(公告)日：2011-01-04
申请号：US12242039
申请日：2008-09-30
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides.
摘要翻译： 一种制造集成电路的方法，该集成电路包括具有栅极间隔物的FET。 一个实施例提供了在薄片的相对侧上形成半导体材料的薄片和两个绝缘体结构。 薄片凹进。 翅片由薄片的中心部分形成。 翅片比在翼片的相对侧上彼此面对的薄片的第一和第二部分薄。 形成第一间隔结构，其包围翅片的第一部分，第一部分与第一薄片部分相邻。 栅电极邻近第一间隔结构设置并且在顶侧和两个相对的侧面上包围翅片的另一部分。
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公开(公告)号：US07622354B2
公开(公告)日：2009-11-24
申请号：US11848857
申请日：2007-08-31
IPC分类号： H01L21/339
CPC分类号： H01L27/10876 , H01L21/84 , H01L21/86 , H01L27/10879 , H01L29/785
摘要： An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transistors of a first type, the transistors of the first type comprising a first gate electrode including vertical portions that are vertically adjacent to a channel of the transistor of the first type.
摘要翻译： 包括存储器件的集成电路包括阵列部分，其包括存储器单元和导电线，导电线的上表面设置在半导体衬底的表面下方，以及支撑部分，包括第一类型的晶体管， 第一类型包括第一栅电极，该第一栅电极包括垂直于第一类型的晶体管的沟道垂直相邻的垂直部分。
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公开(公告)号：US20090057778A1
公开(公告)日：2009-03-05
申请号：US11848857
申请日：2007-08-31
IPC分类号： H01L27/085 , H01L21/8239
CPC分类号： H01L27/10876 , H01L21/84 , H01L21/86 , H01L27/10879 , H01L29/785
摘要： An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transistors of a first type, the transistors of the first type comprising a first gate electrode including vertical portions that are vertically adjacent to a channel of the transistor of the first type.
摘要翻译： 包括存储器件的集成电路包括阵列部分，其包括存储器单元和导电线，导电线的上表面设置在半导体衬底的表面下方，以及支撑部分，包括第一类型的晶体管， 第一类型包括第一栅电极，该第一栅电极包括垂直于第一类型的晶体管的沟道垂直相邻的垂直部分。
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公开(公告)号：US20080283910A1
公开(公告)日：2008-11-20
申请号：US11748864
申请日：2007-05-15
申请人： Lars Dreeskornfeld , Dongping Wu , Jessica Hartwich , Juergen Holz , Arnd Scholz
发明人： Lars Dreeskornfeld , Dongping Wu , Jessica Hartwich , Juergen Holz , Arnd Scholz
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823456 , H01L21/823431 , H01L27/088 , H01L27/0886 , H01L27/1211 , H01L29/66795 , H01L29/66818 , H01L29/785
摘要： An integrated circuit and method of forming an integrated circuit is disclosed. One embodiment includes a FinFET of a first type having a first gate electrode and a FinFET of a second type having a second gate electrode. The first gate electrode is formed in a gate groove that is defined in a semiconductor substrate and a bottom side of a portion of the second gate electrode is disposed above a main surface of the semiconductor substrate.
摘要翻译： 公开了一种形成集成电路的集成电路和方法。 一个实施例包括具有第一栅极和第二类型的具有第二栅电极的FinFET的第一类型的FinFET。 第一栅电极形成在限定在半导体衬底中的栅极沟槽中，并且第二栅电极的一部分的底侧设置在半导体衬底的主表面上方。
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6.发明申请公开(公告)号：US20080296674A1
公开(公告)日：2008-12-04
申请号：US11755141
申请日：2007-05-30
申请人： Andrew Graham , Jessica Hartwich , Arnd Scholz
发明人： Andrew Graham , Jessica Hartwich , Arnd Scholz
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66621 , H01L27/10876 , H01L27/10891 , H01L29/4236 , H01L29/49
摘要： A transistor, an integrated circuit and a method of forming an integrated circuit is disclosed. One embodiment includes a gate electrode. The gate electrode is disposed in a gate groove formed in a semiconductor substrate and includes a conductive carbon material.
摘要翻译： 公开了晶体管，集成电路和形成集成电路的方法。 一个实施例包括栅电极。 栅电极设置在形成在半导体衬底中的栅极沟槽中，并且包括导电碳材料。
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7.发明申请Manufacturing method for forming a recessed channel transistor, method for forming a corresponding integrated semiconductor memory device and corresponding self-aligned mask structure 审中-公开用于形成凹陷沟道晶体管的制造方法，用于形成相应的集成半导体存储器件的方法和相应的自对准掩模结构公开(公告)号：US20080299722A1
公开(公告)日：2008-12-04
申请号：US11807550
申请日：2007-05-29
申请人： Jessica Hartwich , Andrew Graham , Arnd Scholz , Yimin Wang , Stefan Slesazeck , Lars Heineck , Franz Hofmann
发明人： Jessica Hartwich , Andrew Graham , Arnd Scholz , Yimin Wang , Stefan Slesazeck , Lars Heineck , Franz Hofmann
IPC分类号： H01L21/8242
CPC分类号： H01L29/66621 , H01L27/10876 , H01L29/4236 , H01L29/945
摘要： The present invention provides a method for forming a recessed channel transistor comprising the steps of: forming a plurality of active areas lines in a semiconductor substrate with an upper surface, said lines being segmented by segmentation structures having an upper surface height differing from the substrate surface; forming a first and a second extension region arranged above the active area and adjacent said segmentation structures; forming recessed channel devices in the active area segments in the remaining portion of the active area segment between said extension regions.
摘要翻译： 本发明提供了一种用于形成凹陷沟道晶体管的方法，包括以下步骤：在具有上表面的半导体衬底中形成多个有源区线，所述线被具有不同于衬底表面的上表面高度的分割结构分割 ; 形成布置在所述有效区域上方并邻近所述分割结构的第一和第二延伸区域; 在所述延伸区域之间的有源区段的剩余部分中的有源区段中形成凹陷通道器件。
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公开(公告)号：US07867912B2
公开(公告)日：2011-01-11
申请号：US11676635
申请日：2007-02-20
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/3086 , H01L21/3088 , H01L27/0207 , H01L27/1087 , H01L27/115
摘要： A method of manufacturing semiconductor structures is disclosed. In one embodiment, a first mask is provided above a substrate. The first mask includes first mask lines extending along a first axis. A second mask is provided above the first mask. The second mask includes second mask lines extending along a second axis that intersects the first axis. At least one of the first and second masks is formed by a pitch fragmentation method. Structures may be formed in the substrate, wherein the first and the second mask are effective as a combined mask. The structures may be equally spaced at a pitch in the range of a minimum lithographic feature size for repetitive line structures.
摘要翻译： 公开了制造半导体结构的方法。 在一个实施例中，在衬底上方提供第一掩模。 第一掩模包括沿着第一轴线延伸的第一掩模线。 在第一掩模上方提供第二掩模。 第二掩模包括沿着与第一轴相交的第二轴延伸的第二掩模线。 第一和第二掩模中的至少一个由音调分段方法形成。 可以在衬底中形成结构，其中第一和第二掩模作为组合掩模是有效的。 结构可以在重复线结构的最小光刻特征尺寸的范围内以间距等间隔。
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9.发明授权Method for forming inside nitride spacer for deep trench device DRAM cell 失效用于形成深沟槽器件DRAM单元的内部氮化物间隔物的方法公开(公告)号：US06620699B2
公开(公告)日：2003-09-16
申请号：US09967226
申请日：2001-09-28
申请人： Arnd Scholz , Prakash C. Dev
发明人： Arnd Scholz , Prakash C. Dev
IPC分类号： H01L2120
CPC分类号： H01L27/10876 , H01L27/10841 , H01L27/10864 , H01L27/10891 , H01L29/66181
摘要： A method is provided for forming an inside nitride spacer in a deep trench device DRAM cell. The method includes depositing an oxide liner in a trench etched from a semiconductor material, wherein the oxide lines abuts a pad nitride layer, a pad oxide layer under the pad nitride layer, and a recessed gate poly in the trench. The method further includes depositing a spacer material on the oxide liner, removing exposed portions of the oxide layer from the semiconductor, and depositing a poly stud material over the semiconductor wherein the spacer material is encapsulated in poly stud material. The method includes polishing the semiconductor to the top trench oxide layer, and etching the top trench oxide layer.
摘要翻译： 提供了一种用于在深沟槽器件DRAM单元中形成内部氮化物间隔物的方法。 该方法包括在从半导体材料蚀刻的沟槽中沉积氧化物衬垫，其中氧化物线邻接衬垫氮化物层，在衬垫氮化物层下方的衬垫氧化物层和沟槽中的凹陷栅极聚合物。 该方法还包括在氧化物衬垫上沉积间隔物材料，从半导体去除氧化物层的暴露部分，以及在半导体上沉积多晶硅柱材料，其中间隔物材料被包封在聚晶材料中。 该方法包括将半导体抛光到顶部沟槽氧化物层，并蚀刻顶部沟槽氧化物层。
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公开(公告)号：US20090321805A1
公开(公告)日：2009-12-31
申请号：US12165072
申请日：2008-06-30
申请人： Johannes von Kluge , Arnd Scholz , Joerg Radecker , Matthias Patz , Stephan Kudelka , Alejandro Avellan
发明人： Johannes von Kluge , Arnd Scholz , Joerg Radecker , Matthias Patz , Stephan Kudelka , Alejandro Avellan
IPC分类号： H01L27/108 , H01L29/78 , H01L21/28 , H01L21/4763
CPC分类号： H01L29/4236 , H01L21/743 , H01L27/10876 , H01L27/10891 , H01L29/66621
摘要： One embodiment relates to an integrated circuit that includes a conductive line that is arranged in a groove in a semiconductor body. An insulating material is disposed over the conductive line. This insulating material includes a first insulating layer comprising a horizontal portion, and a second insulating layer that is disposed over the first insulating layer. Other methods, devices, and systems are also disclosed.
摘要翻译： 一个实施例涉及一种集成电路，其包括布置在半导体主体中的凹槽中的导线。 绝缘材料设置在导线上。 该绝缘材料包括包括水平部分的第一绝缘层和设置在第一绝缘层上的第二绝缘层。 还公开了其它方法，装置和系统。
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