公开(公告)号：US06190955B1

公开(公告)日：2001-02-20

申请号：US09014433

申请日：1998-01-27

申请人： Matthias Ilg ,  Richard L. Kleinhenz ,  Soichi Nadahara ,  Ronald W. Nunes ,  Klaus Penner ,  Klaus Roithner ,  Radhika Srinivasan ,  Shigeki Sugimoto

发明人： Matthias Ilg ,  Richard L. Kleinhenz ,  Soichi Nadahara ,  Ronald W. Nunes ,  Klaus Penner ,  Klaus Roithner ,  Radhika Srinivasan ,  Shigeki Sugimoto

IPC分类号： H01L218244

CPC分类号： H01L21/3081

摘要： Improved trench forming methods for semiconductor substrates using BSG avoid the problems associated with conventional TEOS hard mask techniques. The methods comprise: (a) providing a semiconductor substrate, (b) applying a conformal layer of borosilicate glass (BSG) on the substrate; (c) forming a patterned photoresist layer over the BSG layer whereby a portion of a layer underlying the photoresist layer is exposed, (d) anisotropically etching through the exposed portion of the underlying layer, through any other layers lying between the photoresist layer and the semiconductor substrate, and into the semiconductor substrate, thereby forming a trench in the semiconductor substrate. Preferably, one or more dielectric layers are present on the substrate surface prior to application of the BSG layer. One or more chemical barrier and/or organic antireflective coating layers may be applied over the BSG layer between the BSG layer and the photoresist layer. The methods are especially useful for forming deep trenches in silicon substrates with pad dielectric layers.

摘要翻译： 使用BSG的半导体衬底的改进的沟槽形成方法避免了与常规TEOS硬掩模技术相关的问题。 所述方法包括：（a）提供半导体衬底，（b）在衬底上施加保形层硼硅酸盐玻璃（BSG）;（c）在BSG层上形成图案化的光刻胶层，由此在光刻胶下面的一部分层 （d）通过位于光致抗蚀剂层和半导体衬底之间的任何其它层，通过底层的暴露部分进行各向异性蚀刻，并进入半导体衬底，由此在半导体衬底中形成沟槽。优选地，一个 或更多的介电层在施加BSG层之前存在于衬底表面上。 可以在BSG层和光致抗蚀剂层之间的BSG层上施加一个或多个化学屏障和/或有机抗反射涂层。 该方法对于在具有焊盘电介质层的硅衬底中形成深沟槽特别有用。

公开(公告)号：US5776808A

公开(公告)日：1998-07-07

申请号：US777156

申请日：1996-12-26

申请人： Karl Paul Muller ,  Bernhard Poschenrieder ,  Klaus Roithner

发明人： Karl Paul Muller ,  Bernhard Poschenrieder ,  Klaus Roithner

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10861 ,  H01L21/31116

摘要： A method for allowing the removal of a TEOS etch mask layer utilizing an anisotropic technique such as reactive ion etching. The use of the anisotropic technique results in substantially less undercutting of the pad oxide layer than wet chemical etching techniques. One embodiment of the invention involves forming a polysilicon etch stop layer under the pad TEOS layer.

摘要翻译： 使用诸如反应离子蚀刻的各向异性技术来允许去除TEOS蚀刻掩模层的方法。 与湿化学蚀刻技术相比，使用各向异性技术导致焊盘氧化物层的底切性更少。 本发明的一个实施例涉及在焊盘TEOS层下面形成多晶硅蚀刻停止层。

公开(公告)号：US06066570A

公开(公告)日：2000-05-23

申请号：US209413

申请日：1998-12-10

申请人： Dung-Ching Perng ,  David M. Dobuzinsky ,  Ting Hao Wang ,  Klaus Roithner

发明人： Dung-Ching Perng ,  David M. Dobuzinsky ,  Ting Hao Wang ,  Klaus Roithner

IPC分类号： H01L21/302 ,  H01L21/20 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/316 ,  H01L21/00

CPC分类号： H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31612

摘要： A method for increasing chip yield by reducing black silicon deposition in accordance with the present invention includes the steps of providing a silicon wafer suitable for fabricating semiconductor chips, depositing a first layer over an entire surface of the wafer, removing a portion of the first layer to expose a region suitable for forming semiconductor devices and etching the wafer such that a remaining portion of the first layer prevents redeposition of etched material on the wafer. A semiconductor assembly for reducing black silicon deposition thereon, includes a silicon wafer suitable for fabricating semiconductor chips, the wafer having a front surface for forming semiconductor devices, a back surface and edges. A deposited layer is formed on the wafer for covering the back surface and the edges such that redeposition of silicon on the back surface and edges of the wafer during etching is prevented.

摘要翻译： 根据本发明的通过减少黑硅沉积来提高芯片产量的方法包括以下步骤：提供适于制造半导体芯片的硅晶片，在晶片的整个表面上沉积第一层，去除第一层的一部分 以暴露适于形成半导体器件的区域并蚀刻晶片，使得第一层的剩余部分防止蚀刻材料在晶片上的再沉积。 一种用于减少黑色硅沉积的半导体组件，包括适于制造半导体芯片的硅晶片，该晶片具有用于形成半导体器件的前表面，后表面和边缘。 在晶片上形成用于覆盖背面和边缘的沉积层，从而防止在蚀刻期间在背面和晶片边缘上再沉积硅。

公开(公告)号：US5961723A

公开(公告)日：1999-10-05

申请号：US756670

申请日：1996-11-26

申请人： Klaus Roithner ,  Bernhard Poschenrieder ,  Karl Paul Muller

发明人： Klaus Roithner ,  Bernhard Poschenrieder ,  Karl Paul Muller

摘要： The present invention is an apparatus for distributing reactant gases across the substrate mounted in a reaction chamber. The apparatus is capable of being utilized in both vapor deposition and etching processes. The apparatus substantially compensates for the problem of non-uniformity of vapor deposition and etching at the edges of the wafers caused by gas depletion. A gas distribution plate having a plurality of apertures extending therethrough is attached to an interior surface of the reaction chamber. At least one vacuum sealed partition is disposed between a surface of the gas distribution plate and the interior surface of the chamber. The partition separates the space between the plate and reaction chamber into gas distribution zones. A gas inlet is connected to each gas distribution zone. Each gas inlet line has at least one mass flow controller which regulates the flow of gas to each gas distribution zone. The mass flow controllers are utilized to ensure a uniform rate of chemical vapor deposition or etching across the surface of the substrate.

公开(公告)号：US06294026B1

公开(公告)日：2001-09-25

申请号：US08756670

申请日：1996-11-26

申请人： Klaus Roithner ,  Bernhard Poschenrieder ,  Karl Paul Muller

发明人： Klaus Roithner ,  Bernhard Poschenrieder ,  Karl Paul Muller

IPC分类号： C23C1600

CPC分类号： C23C16/45565 ,  C23C16/455 ,  C23C16/45561

摘要： The present invention is an apparatus for distributing reactant gases across the substrate mounted in a reaction chamber. The apparatus is capable of being utilized in both vapor deposition and etching processes. The apparatus substantially compensates for the problem of non-uniformity of vapor deposition and etching at the edges of the wafers caused by gas depletion. A gas distribution plate having a plurality of apertures extending therethrough is attached to an interior surface of the reaction chamber. At least one vacuum sealed partition is disposed between a surface of the gas distribution plate and the interior surface of the chamber. The partition separates the space between the plate and reaction chamber into gas distribution zones. A gas inlet is connected to each gas distribution zone. Each gas inlet line has at least one mass flow controller which regulates the flow of gas to each gas distribution zone. The mass flow controllers are utilized to ensure a uniform rate of chemical vapor deposition or etching across the surface of the substrate.

摘要翻译： 本发明是一种用于在反应室内安装反应物气体的装置。 该装置能够用于气相沉积和蚀刻工艺。 该设备基本上补偿了由气体耗尽引起的晶片边缘处气相沉积和蚀刻不均匀的问题。 具有延伸穿过其中的多个孔的气体分配板附接到反应室的内表面。 至少一个真空密封隔板设置在气体分配板的表面和室的内表面之间。 隔板将板和反应室之间的空间分隔成气体分配区。 气体入口连接到每个气体分配区。 每个气体入口管线具有至少一个质量流量控制器，其调节到每个气体分配区域的气体流量。 质量流量控制器用于确保化学气相沉积或蚀刻跨基板表面的均匀速率。

公开(公告)号：US06537418B1

公开(公告)日：2003-03-25

申请号：US08934101

申请日：1997-09-19

申请人： K. Paul Muller ,  Bertrand Flietner ,  Klaus Roithner

发明人： K. Paul Muller ,  Bertrand Flietner ,  Klaus Roithner

IPC分类号： H01L213065

CPC分类号： H01J37/32834 ,  H01J37/3244

摘要： A gas distribution plate (60) for a semiconductor processing chamber (86) includes a gas distribution plate for distributing gases across a surface of a semiconductor wafer (84) to be processed in the chamber. The gas distribution plates has a substantially planar member having gas outlets for distributing a reactant gas across the surface of the semiconductor wafer, the gas outlet means includes a plurality of apertures (66) defined in said planar member, the plurality of apertures having different areas at predetermined locations to adjust etching gas flow. A pump (80) is provided for evacuating a reactant-product gas created across the surface of the semiconductor wafer during wafer processing. The pump (80) includes a plurality of tubes extending through the planar member, the plurality of tubes having apertures, and the apertures have different areas at predetermined locations to adjust reactant gas and reactant-product gas flow wherein the gas outlets and the pump coact to substantially maintain a predetermined concentration of the reactant gas and a predetermined concentration of the reactant-product gas across the surface of the semiconductor wafer during wafer processing.

摘要翻译： 一种用于半导体处理室（86）的气体分配板（60）包括用于在室内分配待处理半导体晶片（84）的表面的气体分配板。 气体分配板具有基本平坦的构件，其具有用于在半导体晶片的表面上分布反应气体的气体出口，气体出口装置包括限定在所述平面构件中的多个孔（66），所述多个孔具有不同的区域 在预定位置调节蚀刻气流。 提供泵（80），用于在晶片处理期间排出在半导体晶片的表面上产生的反应物产物气体。 泵（80）包括延伸穿过平面构件的多个管，多个管具有孔，并且孔在预定位置处具有不同的区域以调节反应气体和反应物产物气流，其中气体出口和泵共同 以在晶片处理期间基本上保持预定浓度的反应气体和预定浓度的反应产物气体跨过半导体晶片的表面。

公开(公告)号：US5592412A

公开(公告)日：1997-01-07

申请号：US539475

申请日：1995-10-05

申请人： Richard Kleinhenz ,  Karl P. Muller ,  Klaus Roithner ,  Masakatsu Tuschiaki

发明人： Richard Kleinhenz ,  Karl P. Muller ,  Klaus Roithner ,  Masakatsu Tuschiaki

IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/8242 ,  H01L29/94 ,  G11C11/24 ,  H01L21/70 ,  H01L29/00

CPC分类号： H01L27/10861 ,  H01L28/82 ,  H01L29/945

摘要： A capacitance storage trench for a DRAM cell includes a trench having at least one sidewall, a bottom wall and a plurality of rods extending away from the bottom wall. The at least one sidewall, the bottom wall and the rods are coated with a capacitive dielectric layer. A layer of semiconductive material is disposed over the dielectric layer. The plurality of rods expand the overall surface area of the trench and thus, provide a significant increase in capacitance storage of the storage trench. The capacitance storage trench is formed in a method which includes the steps of forming a plurality of buried oxygen precipitates in a selected region of a substrate and using the oxygen precipitates as micromasks during a conventional trench etch process.

摘要翻译： 用于DRAM单元的电容存储沟槽包括具有至少一个侧壁，底壁和远离底壁延伸的多个杆的沟槽。 至少一个侧壁，底壁和杆涂覆有电容介电层。 一层半导体材料设置在介电层上。 多个杆扩大沟槽的整个表面积，从而提供存储沟槽的电容存储的显着增加。 电容存储沟槽的形成方法包括以下步骤：在衬底的选定区域中形成多个掩埋的氧沉淀物，并且在常规沟槽蚀刻工艺中使用氧沉淀物作为微取向材料。