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179 条记录 (耗时 0.029 秒)

    Integrated circuit with conductive structures
    2.
    发明授权
    Integrated circuit with conductive structures 有权
    具有导电结构的集成电路

    公开(公告)号：US07893519B2

    公开(公告)日：2011-02-22

    申请号：US12128336

    申请日：2008-05-28

    申请人： Franz Hofmann

    发明人： Franz Hofmann

    IPC分类号： H01L29/00

    CPC分类号： H01L27/11521 ,  H01L27/11524

    摘要： An integrated circuit includes an array of transistors and a number of wordlines, where individual ones of the wordlines are coupled to a number of the transistors in the array. Conductive structures that are insulated from the wordlines are disposed in a layer beneath the wordlines and are arranged between the transistors.

    摘要翻译： 集成电路包括晶体管阵列和多个字线，其中字线中的单个字线与阵列中的多个晶体管耦合。 与字线绝缘的导电结构被布置在字线下方的层中，并且布置在晶体管之间。

    Method of forming a semiconductor memory device and semiconductor memory device
    3.
    发明授权
    Method of forming a semiconductor memory device and semiconductor memory device 有权
    形成半导体存储器件和半导体存储器件的方法

    公开(公告)号：US07767567B2

    公开(公告)日：2010-08-03

    申请号：US11541404

    申请日：2006-09-29

    申请人： Josef Willer ,  Franz Hofmann

    发明人： Josef Willer ,  Franz Hofmann

    IPC分类号： H01L21/3205

    CPC分类号： G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： Gate stacks of an array of memory cells and a plurality of select transistors are formed above a carrier, the gate stacks being separated by spacers. An opening is formed between the spacers in an area that is provided for a source line. A sacrificial layer is applied to fill the opening and is subsequently patterned. Interspaces are filled with a planarizing layer of dielectric material. The residues of the sacrificial layer are removed and an electrically conductive material is applied to form a source line.

    摘要翻译： 存储器单元阵列和多个选择晶体管的栅极堆叠形成在载体上方，栅极堆叠被间隔物隔开。 在为源极线提供的区域中的间隔件之间形成开口。 施加牺牲层以填充开口并且随后被图案化。 间隙填充有介电材料的平坦化层。 去除牺牲层的残余物并施加导电材料以形成源极线。

    Integrated Circuits Having a Contact Region and Methods for Manufacturing the Same
    4.
    发明申请
    Integrated Circuits Having a Contact Region and Methods for Manufacturing the Same 有权
    具有接触区域的集成电路及其制造方法

    公开(公告)号：US20090309152A1

    公开(公告)日：2009-12-17

    申请号：US12137388

    申请日：2008-06-11

    申请人： Roman Knoefler ,  Michael Specht ,  Franz Hofmann ,  Florian Beug ,  Dirk Manger ,  Stephan Riedel

    发明人： Roman Knoefler ,  Michael Specht ,  Franz Hofmann ,  Florian Beug ,  Dirk Manger ,  Stephan Riedel

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

    摘要： In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.

    摘要翻译： 在一个实施例中，提供了具有存储单元布置的集成电路。 存储单元布置可以包括基板，设置在基板上方的散热片结构和存储单元接触区域。 鳍结构可以包括具有多个存储单元结构的存储单元区域，每个存储单元结构具有相应存储单元的有源区域。 此外，存储器单元接触区域可以被配置为电接触每个存储单元结构，其中存储单元接触区域可以包括多个接触区域，这些接触区域在平行于存储器单元结构的方向上相对于彼此至少部分地位移 基材的主要加工表面。

    Method of forming a semiconductor memory device and semiconductor memory device
    5.
    发明申请
    Method of forming a semiconductor memory device and semiconductor memory device 有权
    形成半导体存储器件和半导体存储器件的方法

    公开(公告)号：US20080096352A1

    公开(公告)日：2008-04-24

    申请号：US11541404

    申请日：2006-09-29

    申请人： Josef Willer ,  Franz Hofmann

    发明人： Josef Willer ,  Franz Hofmann

    IPC分类号： H01L21/336

    CPC分类号： G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： Gate stacks of an array of memory cells and a plurality of select transistors are formed above a carrier, the gate stacks being separated by spacers. An opening is formed between the spacers in an area that is provided for a source line. A sacrificial layer is applied to fill the opening and is subsequently patterned. Interspaces are filled with a planarizing layer of dielectric material. The residues of the sacrificial layer are removed and an electrically conductive material is applied to form a source line.

    摘要翻译： 存储器单元阵列和多个选择晶体管的栅极堆叠形成在载体上方，栅极堆叠被间隔物隔开。 在为源极线提供的区域中的间隔件之间形成开口。 施加牺牲层以填充开口并且随后被图案化。 间隙填充有介电材料的平坦化层。 去除牺牲层的残余物并施加导电材料以形成源极线。

    Electronic data memory device for a high read current
    10.
    发明申请
    Electronic data memory device for a high read current 审中-公开
    用于高读取电流的电子数据存储器件

    公开(公告)号：US20060022248A1

    公开(公告)日：2006-02-02

    申请号：US11167386

    申请日：2005-06-27

    申请人： Bjorn Fischer ,  Franz Hofmann ,  Richard Luyken ,  Andreas Spitzer

    发明人： Bjorn Fischer ,  Franz Hofmann ,  Richard Luyken ,  Andreas Spitzer

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10873 ,  H01L29/7851

    摘要： Electronic data memory device for a high read current The invention provides a memory device arranged on a substrate (401) and having at least one memory cell (100) The memory cell comprises a storage capacitor (200) for storing an electrical charge and a selection transistor (300) for selecting the memory cell (100). The selection transistor comprises a first conduction electrode (301), a second conduction electrode (302) and a control electrode (303) , the control electrode (303) being provided by a gate unit (400) having a fin (405) projecting from the substrate (401), which fin is surrounded by a gate oxide layer (406) and a gate electrode layer (403) in such a way that first and second gate elements (408a, 408b) are provided at opposite lateral areas of the fin (405), a third gate element (408c) being provided at an area of the fin (405) that is parallel to the surface of the substrate (401).

    摘要翻译： 用于高读取电流的电子数据存储器件本发明提供一种布置在衬底（401）上并具有至少一个存储单元（100）的存储器件。存储单元包括用于存储电荷的存储电容器（200） 晶体管（300），用于选择存储单元（100）。 选择晶体管包括第一导电电极（301），第二导电电极（302）和控制电极（303），控制电极（303）由栅极单元（400）提供，栅极单元（400）具有从 基板（401），其被栅极氧化物层（406）和栅极电极层（403）包围，使得第一和第二栅极元件（408a，408b）设置在第一和第二栅极元件（408a，408b）的相对侧向区域 所述翅片（405），第三栅极元件（408c）设置在所述鳍状物（405）的与所述基板（401）的表面平行的区域。