-
公开(公告)号：US08664720B2
公开(公告)日：2014-03-04
申请号：US12868434
申请日：2010-08-25
申请人： Mayank Shrivastava , Maryam Shojaei Baghini , Cornelius Christian Russ , Harald Gossner , Ramgopal Rao
发明人： Mayank Shrivastava , Maryam Shojaei Baghini , Cornelius Christian Russ , Harald Gossner , Ramgopal Rao
IPC分类号： H01L29/76 , H01L29/94 , H01L27/01 , H01L27/12 , H01L31/062
CPC分类号： H01L27/1211 , H01L27/0727 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/0847 , H01L29/1033 , H01L29/7831 , H01L29/7835 , H01L29/7836 , H01L29/78624
摘要： In one embodiment, the semiconductor device includes a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first gate region is disposed between the first source and the first drain. A first channel region of a second doping type is disposed under the first gate region. The second doping type is opposite to the first doping type. A first extension region of the first doping type is disposed between the first gate and the first drain. The first extension region is part of a first fin disposed in or over the substrate. A first isolation region is disposed between the first extension region and the first drain. A first well region of the first doping type is disposed under the first isolation region. The first well region electrically couples the first extension region with the first drain.
摘要翻译： 在一个实施例中，半导体器件包括设置在衬底中的第一掺杂类型的第一源。 第一掺杂型的第一漏极设置在衬底中。 第一栅极区域设置在第一源极和第一漏极之间。 第一掺杂类型的第一沟道区域设置在第一栅极区域的下方。 第二掺杂类型与第一掺杂类型相反。 第一掺杂类型的第一延伸区域设置在第一栅极和第一漏极之间。 第一延伸区域是设置在基板中或上方的第一鳍片的一部分。 第一隔离区域设置在第一延伸区域和第一漏极之间。 第一掺杂类型的第一阱区设置在第一隔离区下。 第一阱区域将第一延伸区域与第一漏极电耦合。
-
公开(公告)号：US08455947B2
公开(公告)日：2013-06-04
申请号：US12388479
申请日：2009-02-18
申请人： Mayank Shrivastava , Cornelius Christian Russ , Harald Gossner , Ramgopal Rao , Maryam Shojaei Baghini
发明人： Mayank Shrivastava , Cornelius Christian Russ , Harald Gossner , Ramgopal Rao , Maryam Shojaei Baghini
IPC分类号： H01L29/00
CPC分类号： H01L27/0262 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： This disclosure relates to devices and methods relating to coupled first and second device portions.
摘要翻译： 本公开涉及与耦合的第一和第二设备部分有关的设备和方法。
-
公开(公告)号：US20120049279A1
公开(公告)日：2012-03-01
申请号：US12868434
申请日：2010-08-25
申请人： Mayank Shrivastava , Maryam Shojaei Baghini , Cornelius Christian Russ , Harald Gossner , Ramgopal Rao
发明人： Mayank Shrivastava , Maryam Shojaei Baghini , Cornelius Christian Russ , Harald Gossner , Ramgopal Rao
IPC分类号： H01L27/12
CPC分类号： H01L27/1211 , H01L27/0727 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/0847 , H01L29/1033 , H01L29/7831 , H01L29/7835 , H01L29/7836 , H01L29/78624
摘要： In one embodiment, the semiconductor device includes a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first gate region is disposed between the first source and the first drain. A first channel region of a second doping type is disposed under the first gate region. The second doping type is opposite to the first doping type. A first extension region of the first doping type is disposed between the first gate and the first drain. The first extension region is part of a first fin disposed in or over the substrate. A first isolation region is disposed between the first extension region and the first drain. A first well region of the first doping type is disposed under the first isolation region. The first well region electrically couples the first extension region with the first drain.
摘要翻译： 在一个实施例中，半导体器件包括设置在衬底中的第一掺杂类型的第一源。 第一掺杂型的第一漏极设置在衬底中。 第一栅极区域设置在第一源极和第一漏极之间。 第一掺杂类型的第一沟道区域设置在第一栅极区域的下方。 第二掺杂类型与第一掺杂类型相反。 第一掺杂类型的第一延伸区域设置在第一栅极和第一漏极之间。 第一延伸区域是设置在基板中或上方的第一鳍片的一部分。 第一隔离区域设置在第一延伸区域和第一漏极之间。 第一掺杂类型的第一阱区设置在第一隔离区下。 第一阱区域将第一延伸区域与第一漏极电耦合。
-
公开(公告)号：US20100207161A1
公开(公告)日：2010-08-19
申请号：US12388479
申请日：2009-02-18
申请人： Mayank Shrivastava , Cornelius Christian Russ , Harald Gossner , Ramgopal Rao , Maryam Shojaei Baghini
发明人： Mayank Shrivastava , Cornelius Christian Russ , Harald Gossner , Ramgopal Rao , Maryam Shojaei Baghini
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L27/0262 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： This disclosure relates to devices and methods relating to coupled first and second device portions.
摘要翻译： 本公开涉及与耦合的第一和第二设备部分有关的设备和方法。
-
公开(公告)号：US08536648B2
公开(公告)日：2013-09-17
申请号：US13020368
申请日：2011-02-03
IPC分类号： H01L29/76
CPC分类号： H01L29/1095 , H01L21/26513 , H01L27/088 , H01L29/0634 , H01L29/0642 , H01L29/0653 , H01L29/0847 , H01L29/0873 , H01L29/0878 , H01L29/1054 , H01L29/165 , H01L29/267 , H01L29/41775 , H01L29/45 , H01L29/456 , H01L29/665 , H01L29/66575 , H01L29/66659 , H01L29/78 , H01L29/7816 , H01L29/7835 , H01L29/7842
摘要： In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.
-
6.发明申请公开(公告)号：US20120199878A1
公开(公告)日：2012-08-09
申请号：US13020368
申请日：2011-02-03
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/1095 , H01L21/26513 , H01L27/088 , H01L29/0634 , H01L29/0642 , H01L29/0653 , H01L29/0847 , H01L29/0873 , H01L29/0878 , H01L29/1054 , H01L29/165 , H01L29/267 , H01L29/41775 , H01L29/45 , H01L29/456 , H01L29/665 , H01L29/66575 , H01L29/66659 , H01L29/78 , H01L29/7816 , H01L29/7835 , H01L29/7842
摘要： In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.
摘要翻译： 在本发明的实施例中，半导体器件包括具有第一掺杂类型的第一区域，具有设置在第一区域中的第一掺杂类型的沟道区域和具有第二掺杂类型的逆行阱。 第二掺杂类型与第一掺杂类型相反。 逆行井具有具有第一峰掺杂的较浅层和比第一峰掺杂高的第二峰掺杂的较深层。 该装置还包括在逆行井上具有第二掺杂型的漏极区。 延伸的漏极区域设置在逆行阱中，并且将沟道区域与漏极区域耦合。 隔离区域设置在延伸漏极区域的栅极重叠区域和漏极区域之间。 漏区的长度大于隔离区的深度。
-
公开(公告)号：US09013842B2
公开(公告)日：2015-04-21
申请号：US12987658
申请日：2011-01-10
CPC分类号： H02H9/046 , H01L27/0285 , H01L29/0692 , H01L29/1083
摘要： In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.
摘要翻译： 在一个实施例中，用于在第一节点和第二节点之间提供保护的静电放电（ESD）电路包括具有耦合到第一节点的第一源极/漏极和耦合到中间节点的第二源极/漏极的第一MOS器件 。 ESD电路还包括耦合在第一MOS器件的栅极和第一节点之间的第一电容器，耦合在第一MOS器件的中间节点的栅极之间的第一电阻器，第二MOS / 中间节点和耦合到第二节点的第二源极/漏极，耦合在第二MOS器件的栅极和第一节点之间的第二电容器，以及耦合在第二MOS器件的栅极和第二节点之间的第二电阻器 。
-
公开(公告)号：US20100208405A1
公开(公告)日：2010-08-19
申请号：US12769021
申请日：2010-04-28
CPC分类号： H01L29/735 , H01L27/0262 , H01L29/0615 , H01L29/0619 , H01L29/0692 , H01L29/41708 , H01L29/456 , H01L29/732 , H01L29/7436
摘要： A semiconductor device includes an ESD device region disposed within a semiconductor body of a first semiconductor type, an isolation region surrounding the ESD device region, a first doped region of a second conductivity type disposed at a surface of the semiconductor body within the ESD region, and a second doped region of the first conductivity type disposed between the semiconductor body within the ESD region and at least a portion of the first doped region, where the doping concentration of the second doped region is higher than the semiconductor body. A third doped region of the second semiconductor type is disposed on the semiconductor body and a fourth region of the first conductivity type is disposed over the third doped region. A fifth doped region of the second conductivity type is disposed on the semiconductor body. A trigger device and an SCR is formed therefrom.
摘要翻译： 半导体器件包括设置在第一半导体类型的半导体本体内的ESD器件区域，围绕ESD器件区域的隔离区域，设置在ESD区域内的半导体本体的表面处的第二导电类型的第一掺杂区域， 以及设置在ESD区域内的半导体本体与第一掺杂区域的至少一部分之间的第一导电类型的第二掺杂区域，其中第二掺杂区域的掺杂浓度高于半导体本体。 第二半导体类型的第三掺杂区域设置在半导体本体上，并且第一导电类型的第四区域设置在第三掺杂区域上。 第二导电类型的第五掺杂区域设置在半导体本体上。 触发装置和SCR由其形成。
-
公开(公告)号：US20080179624A1
公开(公告)日：2008-07-31
申请号：US11698674
申请日：2007-01-26
IPC分类号： H01L29/74 , H01L21/332
CPC分类号： H01L29/735 , H01L27/0262 , H01L29/0615 , H01L29/0619 , H01L29/0692 , H01L29/41708 , H01L29/456 , H01L29/732 , H01L29/7436
摘要： A semiconductor device includes an ESD device region disposed within a semiconductor body of a first semiconductor type, an isolation region surrounding the ESD device region, a first doped region of a second conductivity type disposed at a surface of the semiconductor body within the ESD region, and a second doped region of the first conductivity type disposed between the semiconductor body within the ESD region and at least a portion of the first doped region, where the doping concentration of the second doped region is higher than the semiconductor body. A third doped region of the second semiconductor type is disposed on the semiconductor body and a fourth region of the first conductivity type is disposed over the third doped region. A fifth doped region of the second conductivity type is disposed on the semiconductor body. A trigger device and an SCR is formed therefrom.
摘要翻译： 半导体器件包括设置在第一半导体类型的半导体本体内的ESD器件区域，围绕ESD器件区域的隔离区域，设置在ESD区域内的半导体本体的表面处的第二导电类型的第一掺杂区域， 以及设置在ESD区域内的半导体本体与第一掺杂区域的至少一部分之间的第一导电类型的第二掺杂区域，其中第二掺杂区域的掺杂浓度高于半导体本体。 第二半导体类型的第三掺杂区域设置在半导体本体上，并且第一导电类型的第四区域设置在第三掺杂区域上。 第二导电类型的第五掺杂区域设置在半导体本体上。 触发装置和SCR由其形成。
-
10.发明授权Minimum-dimension, fully-silicided MOS driver and ESD protection design for optimized inter-finger coupling 有权最小尺寸，全硅化MOS驱动器和ESD保护设计，实现优化的手指间耦合公开(公告)号：US07005708B2
公开(公告)日：2006-02-28
申请号：US10435817
申请日：2003-05-12
申请人： Markus Paul Josef Mergens , Koen Gerard Maria Verhaege , Cornelius Christian Russ , John Armer , Phillip Czeslaw Jozwiak , Bart Keppens
发明人： Markus Paul Josef Mergens , Koen Gerard Maria Verhaege , Cornelius Christian Russ , John Armer , Phillip Czeslaw Jozwiak , Bart Keppens
IPC分类号： H01L23/62
CPC分类号： H01L27/0277 , H01L29/0692 , H01L29/1083 , H01L29/1087 , H01L29/41758 , H01L29/4238 , H01L29/4975 , H01L29/78 , H01L2224/05554 , H01L2224/48091 , H01L2924/00014
摘要： An electrostatic discharge (ESD) MOS transistor including a plurality of interleaved fingers, where the MOS transistor is formed in an I/O periphery of and integrated circuit (IC) for providing ESD protection for the IC. The MOS transistor includes a P-substrate and a Pwell disposed over the P-substrate. The plurality of interleaved fingers each include an N+ source region, an N+ drain region, and a gate region formed over a channel region disposed between the source and drain regions. Each source and drain includes a row of contacts that is shared by an adjacent finger, wherein each contact hole in each contact row has a distance to the gate region defined under minimum design rules for core functional elements of the IC. The Pwell forms a common parasitic bipolar junction transistor base for contemporaneously triggering each finger of the MOS transistor during an ESD event.
摘要翻译： 一种包括多个交错指状物的静电放电（ESD）MOS晶体管，其中MOS晶体管形成在用于IC的ESD保护的I / O外围和集成电路（IC）中。 MOS晶体管包括设置在P基板上的P基板和Pwell。 多个交错指状物各自包括N +源极区域，N +漏极区域和形成在设置在源极和漏极区域之间的沟道区域上的栅极区域。 每个源极和漏极包括由相邻手指共享的一排触点，其中每个触点行中的每个接触孔具有与IC的核心功能元件的最小设计规则下限定的栅极区域的距离。 Pwell形成一个公共寄生双极结晶体管基极，用于在ESD事件期间同时触发MOS晶体管的每个指状。
-
-
-
-
-
-
-
-
-
搜索结果
46 条记录 (耗时 0.028 秒)
