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1.发明授权Selective deposition of doped silicon-germanium alloy on semiconductor substrate, and resulting structures 失效掺杂硅 - 锗合金在半导体衬底上的选择性沉积，以及所得结构
公开(公告)号：US5336903A
公开(公告)日：1994-08-09
申请号：US69030
申请日：1993-05-28
申请人： Mehmet C. Ozturk , Douglas T. Grider , Mahesh K. Sanganeria , Stanton P. Ashburn , Jimmie J. Wortman
发明人： Mehmet C. Ozturk , Douglas T. Grider , Mahesh K. Sanganeria , Stanton P. Ashburn , Jimmie J. Wortman
IPC分类号： H01L21/225 , H01L21/285 , H01L21/336 , H01L21/60 , H01L23/48
CPC分类号： H01L21/76897 , H01L21/2254 , H01L21/28518 , H01L29/41783 , H01L29/66545 , H01L29/66575 , H01L2924/0002 , Y10S148/058 , Y10S148/059
摘要： Doped silicon-germanium alloy is selectively deposited on a semiconductor substrate, and the semiconductor substrate is then heated to diffuse at least some of the dopant from the silicon-germanium alloy into the semiconductor substrate to form a doped region at the face of the semiconductor substrate. The doped silicon-germanium alloy acts as a diffusion source for the dopant, so that shallow doped, regions may be formed at the face of the semiconductor substrate without ion implantation. A high performance contact to the doped region is also provided by forming a metal layer on the doped silicon-germanium alloy layer and heating to react at least part of the silicon-germanium alloy layer with at least part of the metal layer to form a layer of germanosilicide alloy over the doped regions. The method of the present invention is particularly suitable for forming shallow source and drain regions for a field effect transistor, and self-aligned source and drain contacts therefor.
摘要翻译： 掺杂的硅 - 锗合金被选择性地沉积在半导体衬底上，然后加热半导体衬底以将至少一些掺杂剂从硅 - 锗合金扩散到半导体衬底中，以在半导体衬底的表面形成掺杂区域 。 掺杂的硅 - 锗合金充当掺杂剂的扩散源，使得可以在半导体衬底的表面处形成浅掺杂的区域而不进行离子注入。 还通过在掺杂的硅 - 锗合金层上形成金属层并加热以使至少部分硅 - 锗合金层与至少一部分金属层反应形成层，从而提供与掺杂区的高性能接触 的锗硅酸盐合金。 本发明的方法特别适用于形成用于场效应晶体管的浅源极和漏极区域，以及用于其的自对准源极和漏极接触。
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2.发明授权Selective deposition of doped silion-germanium alloy on semiconductor substrate 失效掺杂硅 - 锗合金在半导体衬底上的选择性沉积
公开(公告)号：US5242847A
公开(公告)日：1993-09-07
申请号：US919735
申请日：1992-07-27
IPC分类号： H01L21/225 , H01L21/285 , H01L21/336 , H01L21/60
CPC分类号： H01L21/76897 , H01L21/2254 , H01L21/28518 , H01L29/41783 , H01L29/66545 , H01L29/66575 , H01L2924/0002 , Y10S148/058 , Y10S148/059
摘要： Doped silicon-germanium alloy is selectively deposited on a semiconductor substrate, and the semiconductor substrate is then heated to diffuse at least some of the dopant from the silicon-germanium alloy into the semiconductor substrate to form a doped region at the face of the semiconductor substrate. The doped silicon-germanium alloy acts as a diffusion source for the dopant, so that shallow doped, regions may be formed at the face of the semiconductor substrate without ion implantation. A high performance contact to the doped region is also provided by forming a metal layer on the doped silicon-germanium alloy layer and heating to react at least part of the silicon-germanium alloy layer with at least part of the metal layer to form a layer of germanosilicide alloy over the doped regions. The method of the present invention is particularly suitable for forming shallow source and drain regions for a field effect transistor, and self-aligned source and drain contacts therefor.
摘要翻译： 掺杂的硅 - 锗合金被选择性地沉积在半导体衬底上，然后加热半导体衬底以将至少一些掺杂剂从硅 - 锗合金扩散到半导体衬底中，以在半导体衬底的表面形成掺杂区域 。 掺杂的硅 - 锗合金充当掺杂剂的扩散源，使得可以在半导体衬底的表面处形成浅掺杂的区域而不进行离子注入。 还通过在掺杂的硅 - 锗合金层上形成金属层并加热以使至少部分硅 - 锗合金层与至少一部分金属层反应形成层，从而提供与掺杂区的高性能接触 的锗硅酸盐合金。 本发明的方法特别适用于形成用于场效应晶体管的浅源极和漏极区域，以及用于其的自对准源极和漏极接触。
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3.发明授权Method for forming a layer of uniform thickness on a semiconductor wafer during rapid thermal processing 失效在快速热处理期间在半导体晶片上形成均匀厚度的层的方法
公开(公告)号：US5439850A
公开(公告)日：1995-08-08
申请号：US117870
申请日：1993-09-08
IPC分类号： C23C16/48 , H01L21/00 , H01L21/205 , H01L21/687
CPC分类号： H01L21/68735 , C23C16/48 , C23C16/481 , H01L21/02381 , H01L21/02395 , H01L21/02488 , H01L21/02532 , H01L21/0262 , H01L21/67109
摘要： A ring is provided on a monocrystalline silicon wafer at one face thereof and adjacent the edge thereof. The ring increases the optical absorptivity of the wafer adjacent the ring compared to the optical absorptivity of the wafer distant from the ring. The ring therefore at least partially compensates for edge cooling of the wafer during rapid thermal processing thereof. Uniform thickness layers can therefore be deposited on a wafer in a rapid thermal processing system. When depositing polycrystalline silicon on an oxide covered layer, the ring may be formed as a circular trench in the oxide layer adjacent the wafer edge.
摘要翻译： 在单晶硅晶片的一个表面上并且在其边缘附近提供环。 与远离环的晶片的光吸收率相比，环增加了与环相邻的晶片的光吸收率。 因此，环在其快速热处理期间至少部分补偿晶片的边缘冷却。 因此，均匀的厚度层可以在快速热处理系统中沉积在晶片上。 当在氧化物覆盖层上沉积多晶硅时，环可以形成为邻近晶片边缘的氧化物层中的圆形沟槽。
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公开(公告)号：US06113984A
公开(公告)日：2000-09-05
申请号：US876967
申请日：1997-06-16
IPC分类号： C23C16/44 , C23C16/455 , C23C16/458 , C23C16/46 , C30B25/10 , C23C16/00
CPC分类号： C23C16/4557 , C23C16/45508 , C23C16/45519 , C23C16/45591 , C23C16/4584 , C23C16/46 , C30B25/08 , C30B25/10
摘要： A CVD reactor includes separate reaction and pressure chambers, where the reaction chamber is contained within and isolates process or reactant gases from the pressure chamber. The reactor also includes a gas injection system which pre-heats and injects diffused process gas(es) into the reaction chamber in a somewhat vertical direction through a bottom surface of the reaction chamber. The gas injection system injects hydrogen or other appropriate gas in a vertical direction through the bottom surface of the reaction chamber. The flow of hydrogen or other appropriate gas is intermediate the flow of the process gas(es) and a surface of the reaction chamber, thereby re-directing the process gas flow parallel to the top surface of a wafer therein. In this manner, the reaction chamber does not require a long entry length for the process gas(es). This flow of hydrogen or other suitable gas also minimizes undesirable deposition on the surface of the reaction chamber.
摘要翻译： CVD反应器包括单独的反应室和压力室，其中反应室被包含在内并且隔离来自压力室的工艺或反应气体。 反应器还包括气体注入系统，其通过反应室的底表面沿着稍微垂直的方向预先加热和注入扩散的工艺气体到反应室中。 气体注入系统通过反应室的底表面沿垂直方向注入氢气或其它合适的气体。 氢或其它合适气体的流动介于工艺气体和反应室的表面之间，从而将工艺气体流平行于晶片的顶表面重新引导。 以这种方式，反应室对于处理气体不需要长的进入长度。 这种氢气或其它合适气体的流动也使反应室表面上不期望的沉积最小化。
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公开(公告)号：US5968279A
公开(公告)日：1999-10-19
申请号：US874851
申请日：1997-06-13
CPC分类号： H01L21/67028
摘要： The silicon surface of a wafer is cleaned at room temperature in a separate pre-clean chamber prior to epitaxial deposition. Fluorine atoms generated, for example, from NF.sub.3 gas, enter the pre-clean chamber, contact the silicon surface, and etch away native oxide, contaminated silicon, and other damage incurred from prior wafer processes. The cleaned wafer is then transferred in an oxygen-free environment to a deposition chamber, for epitaxial deposition. By cleaning at reduced temperatures, autodoping, slip, and other stress-related problems are alleviated. By using a separate chamber for cleaning, system throughput is increased when compared to prior systems using conventional cleaning methods.
摘要翻译： 在外延沉积之前，晶片的硅表面在室温下在单独的预清洁室中被清洁。 例如从NF 3气体产生的氟原子进入预清洁室，接触硅表面，并蚀刻掉原来的氧化物，被污染的硅以及由先前的晶圆工艺引起的其他损坏。 然后将清洁的晶片在无氧环境中转移到沉积室，用于外延沉积。 通过在降低的温度下清洗，减轻自动掺杂，滑移和其他与应力有关的问题。 通过使用单独的室进行清洁，与使用常规清洁方法的现有系统相比，系统吞吐量增加。
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6.发明授权Process for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate by selective deposition on seed layer in patterned trench 失效用于制造集成电路结构的方法，其包括通过在图案化沟槽中的种子层上的选择性沉积形成在半导体衬底上的局部互连
公开(公告)号：US5895261A
公开(公告)日：1999-04-20
申请号：US873809
申请日：1997-06-12
IPC分类号： H01L21/768 , H01L21/441
CPC分类号： H01L21/76879
摘要： A local area interconnect structure comprising one or more electrically conductive interconnects formed from electrically conductive metal compounds is described and a process for forming same. Electrically conductive metal compounds are selectively deposited in one or more trenches which were previously formed in an insulation layer in a configuration conforming to the desired pattern of the electrically conductive interconnects. A seed layer is first selectively formed on surfaces of the trenches and the electrically conductive metal compound is then selectively deposited over the seed layer in the trench, but not on the exposed surfaces of the insulation layer.
摘要翻译： 描述了包括由导电金属化合物形成的一个或多个导电互连的局部互连结构及其形成方法。 导电金属化合物被选择性地沉积在一个或多个沟槽中，其预先形成在符合导电互连的所需图案的构造中的绝缘层中。 首先在沟槽的表面上选择性地形成种子层，然后将导电金属化合物选择性地沉积在沟槽中的种子层上，而不是在绝缘层的暴露表面上沉积。
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公开(公告)号：US06403501B1
公开(公告)日：2002-06-11
申请号：US09748991
申请日：2000-12-27
IPC分类号： H01L2131
CPC分类号： H01L21/02131 , C23C16/4404 , C23C16/4405 , H01L21/02211 , H01L21/02274 , H01L21/31629
摘要： A method is provided that conditions the chamber walls of a HDP CVD reactor by forming a layer of doped material prior to depositing dielectric layers of the doped material onto wafers. A consistent deposition rate can be maintained during subsequent deposition. When deposition is halted, the chamber is cleaned and a thin layer of the doped material is formed on the walls. Consequently, the chamber is kept at equilibrium even during periods of idle, thereby allowing the deposition rates to be consistent even after deposition resumes after the idle periods. For prolonged idle times, the chamber is re-cleaned and the doped material is re-deposited periodically, such as every 12 hours.
摘要翻译： 提供了一种方法，其通过在将掺杂材料的电介质层沉积到晶片上之前形成掺杂材料层来调节HDP CVD反应器的室壁。 在随后的沉积期间可以保持一致的沉积速率。 当沉积停止时，清洁室，并在壁上形成掺杂材料的薄层。 因此，即使在怠速期间，室也保持平衡，从而即使在空闲时段之后恢复沉积之后也能使沉积速率一致。 对于长时间的空闲时间，腔室被重新清洁，并且周期性地重新沉积掺杂的材料，例如每12小时。
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公开(公告)号：US5653808A
公开(公告)日：1997-08-05
申请号：US693721
申请日：1996-08-07
IPC分类号： C23C16/44 , C23C16/455 , C23C16/458 , C23C16/46 , C30B25/10 , C23C16/00
CPC分类号： C23C16/4557 , C23C16/45508 , C23C16/45519 , C23C16/45591 , C23C16/4584 , C23C16/46 , C30B25/08 , C30B25/10
摘要： A CVD reactor includes separate reaction and pressure chambers, where the reaction chamber is contained within and isolates reactant gases from the pressure chamber. The reactor also includes a gas injection system which injects process gas(es) into the reaction chamber in a somewhat vertical direction through a bottom surface of the reaction chamber. The gas injection system injects hydrogen or other appropriate gas in a vertical direction through the bottom surface of the reaction chamber. The flow of hydrogen or other appropriate gas is intermediate the flow of the process gas(es) and a surface of the reaction chamber, thereby re-directing the process gas flow parallel to the top surface of a wafer therein. In this manner, the reaction chamber does not require a long entry length for the process gas(es). This flow of hydrogen or other suitable gas also minimizes undesirable deposition on the surface of the reaction chamber.
摘要翻译： CVD反应器包括单独的反应室和压力室，其中反应室被包含在并分离来自压力室的反应气体。 反应器还包括气体注入系统，其通过反应室的底表面沿着稍微垂直的方向将工艺气体注入反应室。 气体注入系统通过反应室的底表面沿垂直方向注入氢气或其它合适的气体。 氢或其它合适气体的流动介于工艺气体和反应室的表面之间，从而将工艺气体流平行于晶片的顶表面重新引导。 以这种方式，反应室对于处理气体不需要长的进入长度。 这种氢气或其它合适气体的流动也使反应室表面上不期望的沉积最小化。
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公开(公告)号：US6118100A
公开(公告)日：2000-09-12
申请号：US348788
申请日：1999-07-07
IPC分类号： C23C16/458 , C23C16/46 , C30B25/12 , F27B5/14
CPC分类号： C23C16/4584 , C23C16/46 , C30B25/12
摘要： A structure and method for holding a susceptor in a single-wafer RF heated CVD reactor allows the center portion of the susceptor to be heated and prevents susceptor and reactor damage due to overdriving and the susceptor from losing contact with a rotatable rod during thermal expansion. A plug, located on the bottom surface of the susceptor, heated by RF energy subsequently heats the center portion of the susceptor, thereby providing constant temperature gradients across the susceptor. The plug is connected to a rod which is contained in an upper tube and extends into a lower tube. The upper tube is connected to the susceptor via a locking mechanism. An upper spring in the upper tube applies a downward force on the upper tube such that an upward force on the bottom of the susceptor compresses the upper spring, thereby relieving stress on the susceptor and preventing damage due to overdriving. A lower spring is provided within a lower tube connected to the rod such that the lower spring forces the rod upward to keep continual contact with the plug during various times of thermal expansion. The two springs also allow easy removal and assembly of the susceptor and rod structure for cleaning and repair.
摘要翻译： 用于将基座保持在单晶片RF加热CVD反应器中的结构和方法允许基座的中心部分被加热，并且防止由于过度驱动引起的基座和反应器损坏，并且基座在热膨胀期间与可旋转的杆失去接触。 位于基座的底表面上的由RF能量加热的塞子随后加热基座的中心部分，从而在基座上提供恒定的温度梯度。 插头连接到容纳在上管中并延伸到下管中的杆。 上管通过锁定机构连接到基座。 上管中的上弹簧在上管上施加向下的力，使得基座的底部上的向上的力压缩上弹簧，从而减轻基座上的应力并防止由于过度驱动引起的损坏。 下弹簧设置在连接到杆的下管中，使得下弹簧在不同的热膨胀时间期间迫使杆向上以保持与塞的持续接触。 两个弹簧还允许容易地移除和组装用于清洁和修理的基座和杆结构。
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10.发明授权Process for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate by selective deposition on seed layer in patterned trench 失效用于制造集成电路结构的方法，其包括通过在图案化沟槽中的种子层上的选择性沉积形成在半导体衬底上的局部互连
公开(公告)号：US5670425A
公开(公告)日：1997-09-23
申请号：US552461
申请日：1995-11-09
IPC分类号： H01L21/768 , H01L21/441
CPC分类号： H01L21/76879
摘要： A local area interconnect structure comprising one or more electrically conductive interconnects formed from electrically conductive metal compounds is described and a process for forming same. Electrically conductive metal compounds are selectively deposited in one or more trenches which were previously formed in an insulation layer in a configuration conforming to the desired pattern of the electrically conductive interconnects. A seed layer is first selectively formed on surfaces of the trenches and the electrically conductive metal compound is then selectively deposited over the seed layer in the trench, but not on the exposed surfaces of the insulation layer.
摘要翻译： 描述了包括由导电金属化合物形成的一个或多个导电互连的局部互连结构及其形成方法。 导电金属化合物被选择性地沉积在一个或多个沟槽中，其预先形成在符合导电互连的所需图案的构造中的绝缘层中。 首先在沟槽的表面上选择性地形成种子层，然后将导电金属化合物选择性地沉积在沟槽中的种子层上，而不是在绝缘层的暴露表面上沉积。
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