公开(公告)号：US20050239287A1

公开(公告)日：2005-10-27

申请号：US10742202

申请日：2003-12-18

申请人： Mei-Yun Wang ,  Chih-Wei Chang ,  Cheng-Tung Lin ,  Chii-Ming Wu ,  Shau-Lin Shue

发明人： Mei-Yun Wang ,  Chih-Wei Chang ,  Cheng-Tung Lin ,  Chii-Ming Wu ,  Shau-Lin Shue

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/336

CPC分类号： H01L21/28052 ,  H01L21/28518 ,  H01L29/665

摘要： A self-aligned silicide method for integrated circuit and semiconductor device fabrication wherein a metal layer is formed over one or more silicon regions of a substrate and a barrier metal layer is formed over the metal layer using a chemical vapor deposition process. The temperature at which the chemical vapor deposition process is performed causes the metal layer to react with the one or more silicon regions of the substrate to form a metal-silicide film over each of the silicon regions.

摘要翻译： 一种用于集成电路和半导体器件制造的自对准硅化物方法，其中在衬底的一个或多个硅区域上形成金属层，并且使用化学气相沉积工艺在金属层上形成阻挡金属层。 进行化学气相沉积工艺的温度导致金属层与衬底的一个或多个硅区域反应，以在每个硅区域上形成金属硅化物膜。

公开(公告)号：US07015126B2

公开(公告)日：2006-03-21

申请号：US10859730

申请日：2004-06-03

申请人： Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

发明人： Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC分类号： H01L2132/05

CPC分类号： H01L21/28097 ,  H01L21/28518 ,  H01L29/4975 ,  H01L29/66507 ,  H01L29/785

摘要： A method of forming a silicided gate of a field effect transistor on a substrate having active regions is provided. The method includes the following steps: (a) forming a silicide in at least a first portion of a gate; (b) after step (a), depositing a metal over the active regions and said gate; and (c) annealing to cause the metal to react to form silicide in the active regions, wherein the thickness of said gate silicide is greater than the thickness of said silicide in said active regions.

摘要翻译： 提供了在具有有源区的基板上形成场效应晶体管的硅化物栅的方法。 该方法包括以下步骤：（a）在栅极的至少第一部分中形成硅化物; （b）在步骤（a）之后，在有源区域和所述栅极上沉积金属; 和（c）退火以引起金属反应以在有源区中形成硅化物，其中所述栅极硅化物的厚度大于所述有源区中所述硅化物的厚度。

公开(公告)号：US07396767B2

公开(公告)日：2008-07-08

申请号：US10892915

申请日：2004-07-16

申请人： Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

发明人： Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC分类号： H01L21/44

CPC分类号： H01L29/66507 ,  H01L21/28097 ,  H01L29/458 ,  H01L29/4908

摘要： A method of forming a silicided gate on a substrate having active regions, comprising the steps of: forming a first silicide in the active regions from a first material; and forming a second silicide in the gate from a second material, wherein the first silicide forms a barrier against the second material forming a silicide in the active regions during the second silicide forming step, wherein said second silicide is thicker than said first silicide.

摘要翻译： 一种在具有有源区的衬底上形成硅化栅的方法，包括以下步骤：在有源区中从第一材料形成第一硅化物; 以及从所述第二材料在所述栅极中形成第二硅化物，其中所述第一硅化物在所述第二硅化物形成步骤期间在所述有源区中形成抵抗所述第二材料形成硅化物的势垒，其中所述第二硅化物比所述第一硅化物厚。

公开(公告)号：US20060011996A1

公开(公告)日：2006-01-19

申请号：US10892915

申请日：2004-07-16

申请人： Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

发明人： Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC分类号： H01L21/336 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/66507 ,  H01L21/28097 ,  H01L29/458 ,  H01L29/4908

摘要： A method of forming a silicided gate on a substrate having active regions, comprising the steps of: forming a first silicide in the active regions from a first material; and forming a second silicide in the gate from a second material, wherein the first silicide forms a barrier against the second material forming a silicide in the active regions during the second silicide forming step, wherein said second silicide is thicker than said first silicide.

摘要翻译： 一种在具有有源区的衬底上形成硅化栅的方法，包括以下步骤：在有源区中从第一材料形成第一硅化物; 以及从所述第二材料在所述栅极中形成第二硅化物，其中所述第一硅化物在所述第二硅化物形成步骤期间在所述有源区中形成抵抗所述第二材料形成硅化物的势垒，其中所述第二硅化物比所述第一硅化物厚。

公开(公告)号：US20050272235A1

公开(公告)日：2005-12-08

申请号：US10859730

申请日：2004-06-03

申请人： Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

发明人： Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/4763 ,  H01L29/49

CPC分类号： H01L21/28097 ,  H01L21/28518 ,  H01L29/4975 ,  H01L29/66507 ,  H01L29/785

摘要： A method of forming a silicided gate of a field effect transistor on a substrate having active regions is provided. The method includes the following steps: (a) forming a silicide in at least a first portion of a gate; (b) after step (a), depositing a metal over the active regions and said gate; and (c) annealing to cause the metal to react to form silicide in the active regions, wherein the thickness of said gate silicide is greater than the thickness of said silicide in said active regions.

摘要翻译： 提供了在具有有源区的基板上形成场效应晶体管的硅化物栅的方法。 该方法包括以下步骤：（a）在栅极的至少第一部分中形成硅化物; （b）在步骤（a）之后，在有源区域和所述栅极上沉积金属; 和（c）退火以引起金属反应以在有源区中形成硅化物，其中所述栅极硅化物的厚度大于所述有源区中所述硅化物的厚度。

公开(公告)号：US20050092598A1

公开(公告)日：2005-05-05

申请号：US10702970

申请日：2003-11-05

申请人： Mei-Yun Wang ,  Chih-Wei Chang ,  Chii-Ming Wu ,  Cheng-Tung Lin ,  Shau-Lin Shue

发明人： Mei-Yun Wang ,  Chih-Wei Chang ,  Chii-Ming Wu ,  Cheng-Tung Lin ,  Shau-Lin Shue

IPC分类号： C23C14/16 ,  H01L21/285 ,  C23C16/00 ,  C23C14/32

CPC分类号： H01L21/28518 ,  C23C14/16

摘要： A process for reducing the thermal budget and enhancing stability in the thermal budget of a metal salicide process used in the formation of metal salicides on substrates, thus eliminating or reducing salicide spiking and junction leakage in microelectronic devices fabricated on the substrates. According to a typical embodiment, a substrate is cooled to a sub-processing temperature which is lower than the metal deposition processing temperature and the salicide-forming metal is deposited onto the reduced-temperature substrate.

摘要翻译： 一种用于降低热预算并增强用于在基材上形成金属硅化物的金属硅化物工艺的热预算中的稳定性的方法，从而消除或减少在衬底上制造的微电子器件中的自杀剂尖峰和结漏电。 根据典型的实施方式，将基板冷却至比金属沉积处理温度低的副处理温度，并将形成自杀型化合物的金属沉积在还原温度基板上。

公开(公告)号：US20070178696A1

公开(公告)日：2007-08-02

申请号：US11343648

申请日：2006-01-30

申请人： Chii-Ming Wu ,  Shih-Wei Chou ,  Gin Wang ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

发明人： Chii-Ming Wu ,  Shih-Wei Chou ,  Gin Wang ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC分类号： H01L21/44

CPC分类号： H01L21/28518

摘要： A method for forming nickel silicide includes degassing a semiconductor substrate that includes a silicon surface. After the degassing operation, the substrate is cooled prior to a metal deposition process, during a metal deposition process, or both. The cooling suppresses the temperature of the substrate to a temperature less than the temperature required for the formation of nickel silicide. Nickel diffusion is minimized during the deposition process. After deposition, an annealing process is used to urge the formation of a uniform silicide film. In various embodiments, the metal film may include a binary phase alloy containing nickel and a further element.

摘要翻译： 一种形成硅化镍的方法包括对包含硅表面的半导体衬底脱气。 在脱气操作之后，在金属沉积工艺，金属沉积工艺期间或两者之间冷却基板。 冷却将基板的温度抑制到低于形成硅化镍所需的温度的温度。 在沉积过程中镍的扩散最小化。 沉积后，使用退火工艺来促使形成均匀的硅化物膜。 在各种实施例中，金属膜可以包括含有镍和另一元素的二元相合金。

公开(公告)号：US20100151639A1

公开(公告)日：2010-06-17

申请号：US12712518

申请日：2010-02-25

申请人： Shau-Lin Shue ,  Chen-Hua Yu ,  Cheng-Tung Lin ,  Chii-Ming Wu ,  Shih-Wei Chou ,  Gin Jei Wang ,  CP Lo ,  Chih-Wei Chang

发明人： Shau-Lin Shue ,  Chen-Hua Yu ,  Cheng-Tung Lin ,  Chii-Ming Wu ,  Shih-Wei Chou ,  Gin Jei Wang ,  CP Lo ,  Chih-Wei Chang

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L29/665 ,  H01L21/76243 ,  H01L29/785

摘要： Provided is a method of fabrication a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, the gate structure including a gate dielectric and a gate electrode disposed over the gate dielectric, forming source/drain regions in the semiconductor substrate at either side of the gate structure, forming a metal layer over the semiconductor substrate and the gate structure, the metal layer including a refractory metal layer or a refractory metal compound layer; forming an alloy layer over the metal layer; and performing an annealing thereby forming metal alloy silicides over the gate structure and the source/drain regions, respectively.

摘要翻译： 提供一种制造半导体器件的方法，其包括提供半导体衬底，在衬底上形成栅极结构，栅极结构包括栅极电介质和设置在栅极电介质上的栅电极，在半导体衬底中形成源极/漏极区域 在栅极结构的任一侧，在半导体衬底和栅极结构之上形成金属层，金属层包括难熔金属层或难熔金属化合物层; 在所述金属层上形成合金层; 并进行退火，从而分别在栅极结构和源极/漏极区域上形成金属合金硅化物。

公开(公告)号：US20080070370A1

公开(公告)日：2008-03-20

申请号：US11523678

申请日：2006-09-19

申请人： Chii-Ming Wu ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

发明人： Chii-Ming Wu ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC分类号： H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/2658 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/78654

摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a gate stack on the semiconductor substrate, forming a silicon-containing compound stressor adjacent the gate stack, implanting non-siliciding ions into the silicon-containing compound stressor to amorphize an upper portion of the silicon-containing compound stressor, forming a metal layer on the silicon-containing compound stressor while the upper portion of the SiGe stressor is amorphous, and annealing to react the metal layer with the silicon-containing compound stressor to form a silicide region. The silicon-containing compound stressor includes SiGe or SiC.

摘要翻译： 一种用于形成半导体结构的方法包括：提供半导体衬底，在半导体衬底上形成栅极叠层，在栅堆叠附近形成含硅化合物应力源，将非硅化离子注入到含硅化合物应力器中以使上层 部分含硅化合物应激源，在含硅化合物应激源上形成金属层，同时SiGe应力源的上部为无定形，退火以使金属层与含硅化合物应激源反应形成硅化物区域 。 含硅化合物应激源包括SiGe或SiC。

公开(公告)号：US07625801B2

公开(公告)日：2009-12-01

申请号：US11523678

申请日：2006-09-19

申请人： Chii-Ming Wu ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

发明人： Chii-Ming Wu ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC分类号： H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/2658 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/78654

摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a gate stack on the semiconductor substrate, forming a silicon-containing compound stressor adjacent the gate stack, implanting non-siliciding ions into the silicon-containing compound stressor to amorphize an upper portion of the silicon-containing compound stressor, forming a metal layer on the silicon-containing compound stressor while the upper portion of the SiGe stressor is amorphous, and annealing to react the metal layer with the silicon-containing compound stressor to form a silicide region. The silicon-containing compound stressor includes SiGe or SiC.

摘要翻译： 一种用于形成半导体结构的方法包括：提供半导体衬底，在半导体衬底上形成栅极叠层，在栅堆叠附近形成含硅化合物应力源，将非硅化离子注入到含硅化合物应力器中以使上层 含硅化合物应激源的部分，在含硅化合物应激物上形成金属层，同时SiGe应力源的上部是无定形的，退火使金属层与含硅化合物应激反应物形成硅化物区域 。 含硅化合物应激源包括SiGe或SiC。