公开(公告)号：US07417329B2

公开(公告)日：2008-08-26

申请号：US11420230

申请日：2006-05-25

申请人： Meng-Jung Chuang ,  Cheng-Yin Lee ,  Wei-Chang Tai ,  Chi-Chih Chu

发明人： Meng-Jung Chuang ,  Cheng-Yin Lee ,  Wei-Chang Tai ,  Chi-Chih Chu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K3/284 ,  H05K3/3452 ,  H05K2203/0588 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A system-in-package structure includes a carrier substrate having a molding area and a periphery area, at least a chip disposed in the molding area, an encapsulation covering the chip and the molding area, a plurality of solder pads disposed in the periphery area, and a solder mask disposed in the periphery area and partially exposing the surface of the solder pads. The solder mask includes at least a void therein.

摘要翻译： 系统级封装结构包括具有成型区域和周边区域的载体基板，至少设置在模制区域中的芯片，覆盖芯片和模制区域的封装，设置在外围区域中的多个焊盘 以及设置在周边区域中并部分地暴露焊盘表面的焊接掩模。 焊料掩模至少包括其中的空隙。

公开(公告)号：US07473629B2

公开(公告)日：2009-01-06

申请号：US11634059

申请日：2006-12-06

申请人： Wei-Chang Tai ,  Chi-Chih Chu ,  Meng-Jung Chuang ,  Cheng-Yin Lee ,  Yao-Ting Huang ,  Kuang-Lin Lo

发明人： Wei-Chang Tai ,  Chi-Chih Chu ,  Meng-Jung Chuang ,  Cheng-Yin Lee ,  Yao-Ting Huang ,  Kuang-Lin Lo

IPC分类号： H01L21/44

CPC分类号： H05K3/3452 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H05K3/284 ,  H05K2203/0588 ,  H01L2924/00014 ,  H01L2924/00

摘要： A substrate structure having a solder mask and a process for making the same, including (a) providing a substrate having a top surface, the top surface having a die pad and a plurality of solder pads; (b) forming a first solder mask on the top surface, the first solder mask having a plurality of openings, each opening corresponding to each solder pad so as to expose at least part of the solder pad; and (c) forming a second solder mask on the first solder mask. The substrate structure can be used for packaging a thicker die so as to prevent the die crack and the overflow of molding compound will be avoided.

摘要翻译： 一种具有焊料掩模的衬底结构及其制造方法，包括：（a）提供具有顶表面的衬底，所述顶表面具有管芯焊盘和多个焊盘; （b）在所述顶表面上形成第一焊料掩模，所述第一焊料掩模具有多个开口，每个开口对应于每个焊盘，以暴露所述焊盘的至少一部分; 和（c）在第一焊料掩模上形成第二焊料掩模。 衬底结构可用于包装较厚的模具，以防止模具裂纹，并避免模塑料的溢流。

公开(公告)号：US20070243704A1

公开(公告)日：2007-10-18

申请号：US11634059

申请日：2006-12-06

申请人： Wei-Chang Tai ,  Chi-Chih Chu ,  Meng-Jung Chuang ,  Cheng-Yin Lee ,  Yao-Ting Huang ,  Kuang-Lin Lo

发明人： Wei-Chang Tai ,  Chi-Chih Chu ,  Meng-Jung Chuang ,  Cheng-Yin Lee ,  Yao-Ting Huang ,  Kuang-Lin Lo

IPC分类号： H01L21/44

CPC分类号： H05K3/3452 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H05K3/284 ,  H05K2203/0588 ,  H01L2924/00014 ,  H01L2924/00

摘要： The present invention relates to a substrate structure having a solder mask and a process for making the same. The process comprises: (a) providing a substrate having a top surface, the top surface having a die pad and a plurality of solder pads; (b) forming a first solder mask on the top surface, the first solder mask having a plurality of openings, each opening corresponding to each solder pad so as to expose at least part of the solder pad; and (c) forming a second solder mask on the first solder mask. Whereby, the substrate structure of the invention can be used for packaging a thicker die so as to prevent the die crack and the overflow of molding compound will be avoided.

摘要翻译： 本发明涉及一种具有焊接掩模的基片结构及其制造方法。 该方法包括：（a）提供具有顶表面的基底，顶表面具有管芯焊盘和多个焊盘; （b）在所述顶表面上形成第一焊料掩模，所述第一焊料掩模具有多个开口，每个开口对应于每个焊盘，以暴露所述焊盘的至少一部分; 和（c）在第一焊料掩模上形成第二焊料掩模。 由此，本发明的基板结构可以用于包装较厚的模具，以防止模具裂纹，并避免模塑料的溢流。

公开(公告)号：US20070132093A1

公开(公告)日：2007-06-14

申请号：US11420230

申请日：2006-05-25

申请人： Meng-Jung Chuang ,  Cheng-Yin Lee ,  Wei-Chang Tai ,  Chi-Chih Chu

发明人： Meng-Jung Chuang ,  Cheng-Yin Lee ,  Wei-Chang Tai ,  Chi-Chih Chu

IPC分类号： H01L23/34

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K3/284 ,  H05K3/3452 ,  H05K2203/0588 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A system-in-package structure includes a carrier substrate having a molding area and a periphery area, at least a chip disposed in the molding area, an encapsulation covering the chip and the molding area, a plurality of solder pads disposed in the periphery area, and a solder mask disposed in the periphery area and partially exposing the surface of the solder pads. The solder mask includes at least a void therein.

摘要翻译： 系统级封装结构包括具有成型区域和周边区域的载体基板，至少设置在模制区域中的芯片，覆盖芯片和模制区域的封装，设置在外围区域中的多个焊盘 以及设置在周边区域中并部分地暴露焊盘表面的焊接掩模。 焊料掩模至少包括其中的空隙。

公开(公告)号：US20080076208A1

公开(公告)日：2008-03-27

申请号：US11828352

申请日：2007-07-26

申请人： Yen-Yi Wu ,  Wei-Yueh Sung ,  Pao-Huei Chang Chien ,  Chi-Chih Chu ,  Cheng-Yin Lee ,  Gwo-Liang Weng

发明人： Yen-Yi Wu ,  Wei-Yueh Sung ,  Pao-Huei Chang Chien ,  Chi-Chih Chu ,  Cheng-Yin Lee ,  Gwo-Liang Weng

IPC分类号： H01L21/00

CPC分类号： H01L24/14 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/1405 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention relates to a semiconductor package and a semiconductor device and a method of making the same. The method of making the semiconductor package comprises: providing a substrate; attaching a chip to a surface of the substrate; forming a plurality of connecting elements for electrically connecting the chip and the substrate; forming a plurality of first conductive bodies on the surface of the substrate; forming a molding compound for encapsulating the surface of the substrate, the chip, the connecting elements and the first conductive bodies; and removing a part of a border portion of the molding compound, so that the molding compound has two heights and one end of each first conductive bodies is exposed. Thereby, the molding compound covers the entire surface of the substrate, so that the bonding pads on the surface of the substrate will not be polluted.

摘要翻译： 本发明涉及半导体封装和半导体器件及其制造方法。 制造半导体封装的方法包括：提供衬底; 将芯片附接到所述基板的表面; 形成用于电连接所述芯片和所述基板的多个连接元件; 在所述基板的表面上形成多个第一导电体; 形成用于封装基板，芯片，连接元件和第一导电体的表面的模塑料; 并且除去模塑料的边界部分的一部分，使得模塑料具有两个高度，并且暴露出每个第一导电体的一端。 因此，成型化合物覆盖基板的整个表面，使得基板表面上的接合焊盘不会被污染。

公开(公告)号：US07642133B2

公开(公告)日：2010-01-05

申请号：US11828352

申请日：2007-07-26

申请人： Yen-Yi Wu ,  Wei-Yueh Sung ,  Pao-Huei Chang Chien ,  Chi-Chih Chu ,  Cheng-Yin Lee ,  Gwo-Liang Weng

发明人： Yen-Yi Wu ,  Wei-Yueh Sung ,  Pao-Huei Chang Chien ,  Chi-Chih Chu ,  Cheng-Yin Lee ,  Gwo-Liang Weng

IPC分类号： H01L21/00 ,  H01L21/44 ,  H01L23/02

CPC分类号： H01L24/14 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/1405 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention relates to a semiconductor package and a semiconductor device and a method of making the same. The method of making the semiconductor package comprises: providing a substrate; attaching a chip to a surface of the substrate; forming a plurality of connecting elements for electrically connecting the chip and the substrate; forming a plurality of first conductive bodies on the surface of the substrate; forming a molding compound for encapsulating the surface of the substrate, the chip, the connecting elements and the first conductive bodies; and removing a part of a border portion of the molding compound, so that the molding compound has two heights and one end of each first conductive bodies is exposed. Thereby, the molding compound covers the entire surface of the substrate, so that the bonding pads on the surface of the substrate will not be polluted.

摘要翻译： 本发明涉及半导体封装和半导体器件及其制造方法。 制造半导体封装的方法包括：提供衬底; 将芯片附接到所述基板的表面; 形成用于电连接所述芯片和所述基板的多个连接元件; 在所述基板的表面上形成多个第一导电体; 形成用于封装基板，芯片，连接元件和第一导电体的表面的模塑料; 并且除去模塑料的边界部分的一部分，使得模塑料具有两个高度，并且暴露出每个第一导电体的一端。 因此，成型化合物覆盖基板的整个表面，使得基板表面上的接合焊盘不会被污染。

公开(公告)号：US20080073769A1

公开(公告)日：2008-03-27

申请号：US11828351

申请日：2007-07-26

申请人： Yen-Yi Wu ,  Wei-Yueh Sung ,  Pao-Huei Chang Chien ,  Chi-Chih Chu ,  Cheng-Yin Lee ,  Gwo-Liang Weng

发明人： Yen-Yi Wu ,  Wei-Yueh Sung ,  Pao-Huei Chang Chien ,  Chi-Chih Chu ,  Cheng-Yin Lee ,  Gwo-Liang Weng

IPC分类号： H01L23/02 ,  H01L23/52

CPC分类号： H01L24/14 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/1405 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention relates to a semiconductor package and a semiconductor device and a method of making the same. The method of making the semiconductor package comprises: providing a substrate; attaching a chip to a surface of the substrate; forming a plurality of connecting elements for electrically connecting the chip and the substrate; forming a plurality of first conductive bodies on the surface of the substrate; forming a molding compound for encapsulating the surface of the substrate, the chip, the connecting elements and the first conductive bodies; and removing a part of a border portion of the molding compound, so that the molding compound has two heights and one end of each first conductive bodies is exposed. Thereby, the molding compound covers the entire surface of the substrate, so that the bonding pads on the surface of the substrate will not be polluted.

摘要翻译： 本发明涉及半导体封装和半导体器件及其制造方法。 制造半导体封装的方法包括：提供衬底; 将芯片附接到所述基板的表面; 形成用于电连接所述芯片和所述基板的多个连接元件; 在所述基板的表面上形成多个第一导电体; 形成用于封装基板，芯片，连接元件和第一导电体的表面的模塑料; 并且除去模塑料的边界部分的一部分，使得模塑料具有两个高度，并且暴露出每个第一导电体的一端。 因此，成型化合物覆盖基板的整个表面，使得基板表面上的接合焊盘不会被污染。

公开(公告)号：US07187070B2

公开(公告)日：2007-03-06

申请号：US10934409

申请日：2004-09-07

申请人： Chi Chih Chu ,  Cheng-Yin Lee ,  Gwo-Liang Weng ,  Shih-Chang Lee

发明人： Chi Chih Chu ,  Cheng-Yin Lee ,  Gwo-Liang Weng ,  Shih-Chang Lee

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L2224/16145 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/18161

摘要： A Stackable package module comprises a plurality of semiconductor devices in stack. One of the semiconductor devices includes a chip with an active surface and a corresponding back surface, a plurality of solder bumps and a plurality of stud bumps. The solder bumps are formed on the active surface. The stud bumps are formed on the back surface. Each stud bump has a bump body and a protruding trail by wire-bonding and cutting. Bumps of another package are bonded on the stub bumps for replacing known intermediate substrate in conventional stacked package module.

摘要翻译： 可堆叠封装模块包括堆叠中的多个半导体器件。 半导体器件中的一个包括具有活性表面和对应的背面的芯片，多个焊料凸块和多个凸块凸块。 焊料凸块形成在有源表面上。 柱形凸块形成在背面。 每个柱形凸起具有凸起体和通过引线接合和切割的突出轨迹。 另一个封装的凸块被结合在短截线凸起上，用于替代传统堆叠封装模块中的已知中间衬底。

公开(公告)号：US20050181543A1

公开(公告)日：2005-08-18

申请号：US10907561

申请日：2005-04-06

申请人： Shih-Chang Lee ,  Gwo-Liang Weng ,  Wei-Chang Tai ,  Cheng-Yin Lee

发明人： Shih-Chang Lee ,  Gwo-Liang Weng ,  Wei-Chang Tai ,  Cheng-Yin Lee

IPC分类号： H01L23/31 ,  H01L25/065 ,  H01L25/10 ,  H05K1/18 ,  H05K3/28 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/48

CPC分类号： H01L23/3121 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0655 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/181 ,  H05K3/284 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A process for fabricating a multi-chip package module is disclosed. A substrate, at least a first chip and at least a second chip are provided. The backside of the first chip is attached to a die pad on a substrate. A wire-bonding operation is carried out to electrically connect the first chip and the substrate through conductive wires. A plurality of bumps is bonded to the second chip so that one end of each bump is bonded to a contact on the second chip. Thereafter, the other end of each bump is bonded to a contact on the substrate so that the second chip and the substrate are physically and electrically connected together. Finally, an encapsulation process is performed to form a packaging material enclosing the first chip, the second chip, the conductive wires, the bumps and the substrate.

摘要翻译： 公开了一种用于制造多芯片封装模块的工艺。 提供基板，至少第一芯片和至少第二芯片。 第一芯片的背面连接到基板上的芯片焊盘。 进行引线接合操作，以通过导线将第一芯片和基板电连接。 将多个凸块接合到第二芯片，使得每个凸块的一端接合到第二芯片上的触点。 此后，每个凸块的另一端结合到基板上的接触件，使得第二芯片和基板物理和电连接在一起。 最后，进行包封处理以形成封装第一芯片，第二芯片，导线，凸块和基板的封装材料。

公开(公告)号：US20060110849A1

公开(公告)日：2006-05-25

申请号：US11210700

申请日：2005-08-25

申请人： Cheng-Yin Lee ,  Wei-Chang Tai

发明人： Cheng-Yin Lee ,  Wei-Chang Tai

IPC分类号： H01L21/00

CPC分类号： H01L25/50 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K3/3436 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： The present invention relates to a method for stacking BGA packages. At first, a first BGA package is provided. The first BGA package includes a first substrate, at least one first chip and a plurality of first connecting balls. The first substrate has a first upper surface and a first bottom surface. The first chip is disposed on the first upper surface. The first connecting balls are disposed on a plurality of first connecting pads of the first upper surface. Then, a second BGA package is provided. The second BGA package includes a second substrate, at least one second chip and a plurality of second connecting balls. The second substrate has a second upper surface and a second bottom surface. The second connecting balls are disposed on a plurality of second connecting pads of the second bottom surface. The second BGA package is stacked on the first BGA package for the second connecting balls to contact the corresponding first connecting balls. Then, the first connecting balls and the corresponding second connecting balls are reflowed into a plurality of integrated spacer balls. The spacer balls connect the first connecting pads and the second connecting pads for providing a stack gap.

摘要翻译： 本发明涉及一种用于堆叠BGA封装的方法。 首先，提供了第一个BGA封装。 第一BGA封装包括第一衬底，至少一个第一芯片和多个第一连接球。 第一基板具有第一上表面和第一底表面。 第一芯片设置在第一上表面上。 第一连接球设置在第一上表面的多个第一连接焊盘上。 然后，提供第二个BGA封装。 第二BGA封装包括第二衬底，至少一个第二芯片和多个第二连接球。 第二基板具有第二上表面和第二底表面。 第二连接球设置在第二底面的多个第二连接垫上。 第二个BGA封装堆叠在第一个BGA封装上，用于第二个连接球接触相应的第一个连接球。 然后，将第一连接球和相应的第二连接球回流到多个集成的间隔球。 间隔球连接第一连接焊盘和第二连接焊盘，以提供堆叠间隙。