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    Semiconductor device having dual-gate transistors and calibration circuitry
    1.
    发明授权
    Semiconductor device having dual-gate transistors and calibration circuitry 有权

    公开(公告)号：US09601167B1

    公开(公告)日：2017-03-21

    申请号：US14665711

    申请日：2015-03-23

    申请人： Michael C. Stephens, Jr.

    发明人： Michael C. Stephens, Jr.

    IPC分类号： G11C7/08 ,  G11C7/06

    CPC分类号： H03K17/284 ,  G05F1/468 ,  G11C7/065 ,  G11C7/08 ,  G11C7/22 ,  G11C29/026 ,  G11C29/028 ,  H03K17/302 ,  H03K17/687 ,  H03K17/6871 ,  H03K2017/6878

    摘要： Disclosed are various embodiments related to dual-gate transistors and associated calibration circuitry. In one embodiment, dual-gate transistors may be configured in a sense amplifier arrangement, and calibration circuitry can be used to adjust an input offset of the sense amplifier. In another embodiment, a reference level voltage utilized in an amplifier with dual-gate transistors can be adjusted during a calibration sequence, and may be substantially unchanged from its nominal value outside of the calibration sequence. In another embodiment, a calibration sequence can be utilized to determine circuit results from a circuit including dual-gate transistors, and to adjust control gates to more closely coincide with expected or desired results. In yet another embodiment, a semiconductor memory device can include a memory array with amplifiers that include dual-gate transistors, as well as associated calibration circuitry.

    Compare circuit and method for content addressable memory (CAM) device
    2.
    发明授权
    Compare circuit and method for content addressable memory (CAM) device 失效
    内容可寻址存储器（CAM）器件的比较电路和方法

    公开(公告)号：US06988164B1

    公开(公告)日：2006-01-17

    申请号：US10320588

    申请日：2002-12-16

    申请人： Sanlay M. Wanzakhade ,  Michael C. Stephens, Jr.

    发明人： Sanlay M. Wanzakhade ,  Michael C. Stephens, Jr.

    IPC分类号： G06F12/00

    CPC分类号： G11C15/00

    摘要： A content addressable memory (CAM) device (100) may include a number of sub-blocks (102-8 to 102-15) that can generate CAM search results. In a “search beyond” operation, sub-blocks (102-8 to 102-15) may be excluded from a search operation according to criteria, including a sub-block address and a soft-priority value. A CAM device may include a compare circuit (400) that may compare sub-block address values in a time division multiplexed fashion to establish priority from among multiple CAM sub-blocks.

    摘要翻译： 内容可寻址存储器（CAM）设备（100）可以包括可以生成CAM搜索结果的多个子块（102-8至102-15）。 在“搜索超出”操作中，可以根据包括子块地址和软优先级值的标准从搜索操作中排除子块（102-8至102-15）。 CAM设备可以包括比较电路（400），其可以以时分多路复用的方式比较子块地址值，以从多个CAM子块中建立优先级。

    Result compare circuit and method for content addressable memory (CAM) device
    4.
    发明授权
    Result compare circuit and method for content addressable memory (CAM) device 失效
    内容寻址存储器（CAM）设备的结果比较电路和方法

    公开(公告)号：US06845024B1

    公开(公告)日：2005-01-18

    申请号：US10317918

    申请日：2002-12-12

    申请人： Sanjay M. Wanzakhade ,  Michael C. Stephens, Jr. ,  Jagadeesan Rajamanickam ,  David V. James

    发明人： Sanjay M. Wanzakhade ,  Michael C. Stephens, Jr. ,  Jagadeesan Rajamanickam ,  David V. James

    IPC分类号： G11C15/00

    CPC分类号： G11C15/00

    摘要： A content addressable memory (CAM) device (100) may include a number of blocks (102-[n−1, n, n+1]) that each generate CAM search results and result compare circuits (104-[n−1, n, n+1] that receive CAM search results from multiple blocks (102-[n−1, n, n−1]), and compare at least a portion of such CAM search results. According to such a comparison result, a compare circuit (104-[n−1, n, n+1]) can generate an output CAM search result for subsequent comparison with CAM search result in another compare circuit (104-[n−1, n, n+1]).

    摘要翻译： 内容可寻址存储器（CAM）装置（100）可以包括多个块（102- [n-1，n，n + 1]），每个块生成CAM搜索结果和结果比较电路（104- [n-1，n， n，n + 1]，从多个块（102- [n-1，n，n-1]）接收CAM搜索结果，并比较这些CAM搜索结果的至少一部分，根据这样的比较结果， 比较电路（104- [n-1，n，n + 1]）可以生成输出CAM搜索结果，用于随后与另一比较电路（104- [n-1，n，n + 1]）中的CAM搜索结果进行比较 。

    Internal charge pump voltage limit control
    5.
    发明授权
    Internal charge pump voltage limit control 有权
    内部电荷泵电压限制控制

    公开(公告)号：US06208197B1

    公开(公告)日：2001-03-27

    申请号：US09262503

    申请日：1999-03-04

    申请人： Luigi Ternullo, Jr. ,  Michael C. Stephens, Jr.

    发明人： Luigi Ternullo, Jr. ,  Michael C. Stephens, Jr.

    IPC分类号： G05F110

    CPC分类号： H02M3/07

    摘要： A charge pump limits the voltages at nodes internal to the charge pump to reduce the risk of junction breakdown in the charge pump. The charge pump includes a first pump circuit, a second pump circuit, a first clamp and a second clamp. The first clamp limits the voltage level of a well by providing a current path from the well to the output lead when the voltage level of the well reaches a first predetermined limit. The voltage level at a node from which charge is redistributed to the well is limited by the second clamp, which is configured to provide a conductive path from the node to the output lead when the voltage level of the node reaches a second predetermined limit. The pump circuits can each include a logic circuit that is configured, depending on the level of an external supply voltage, to reduce the rate at which the capacitor node is boosted when the external supply voltage is relatively high. The logic circuit can also vary the voltage difference between the capacitor node and the external supply voltage to decrease the relative voltage level at the capacitor node relative to the level of the external supply voltage. These features also help reduce the risk of junction breakdown in the charge pump.

    摘要翻译： 电荷泵限制电荷泵内部节点处的电压，以降低电荷泵中结点破裂的风险。 电荷泵包括第一泵电路，第二泵电路，第一夹具和第二夹具。 当阱的电压水平达到第一预定极限时，第一钳位器通过提供从井到输出引线的电流路径来限制阱的电压电平。 电荷再分配到阱的节点处的电压电平受到第二钳位限制，第二钳位器被配置为当节点的电压电平达到第二预定极限时，提供从节点到输出引线的导电路径。 泵电路可以各自包括根据外部电源电压的电平配置的逻辑电路，以在外部电源电压相对较高时降低电容器节点升压的速率。 逻辑电路还可以改变电容器节点和外部电源电压之间的电压差，以降低电容器节点处的相对电压相对于外部电源电压的电平。 这些功能还有助于降低电荷泵中结点破裂的风险。

    High-speed synchronous write control scheme
    6.
    发明授权
    High-speed synchronous write control scheme 失效
    高速同步写控制方案

    公开(公告)号：US06052328A

    公开(公告)日：2000-04-18

    申请号：US995379

    申请日：1997-12-22

    申请人： Luigi Ternullo, Jr. ,  Michael C. Stephens, Jr.

    发明人： Luigi Ternullo, Jr. ,  Michael C. Stephens, Jr.

    IPC分类号： G11C8/00 ,  G11C11/401

    CPC分类号： G11C7/1048 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4096 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/222

    摘要： The present invention provides a method and apparatus that accomplishes a high performance, random read/write SDRAM design by synchronizing the read and write operations at the data line sense amplifier. This enables the design to perform random read and write operations without varying cycle time issues or unbalanced margin issues. The data lines are used as bi-directional lines to accomplish high performance reads and writes with minimal additional wiring overhead required. During a read operation, read data is transferred from the memory cells of the device across a series of consecutive pairs of data lines to an input/output port of the memory device. The first pair of data lines is coupled to a data line sense amplifier. The additional pairs of data lines are coupled to additional amplifiers. During a read operation, data is transferred across the consecutive pairs of data lines according to the timing cycles of the respective amplifiers. In order to quickly drive the data signals during a write operation up the series of consecutive pairs of data lines, the timing signals for each of the pairs of data lines except the first pair of data lines are disabled so that the data lines are allowed to float, and then the data lines are overdriven with the write data so that the write data quickly transitions up the series of data lines to the selected data line sense amplifier, where it arrives at approximately the same time that read data normally arrives during the timing cycle for the data line sense amplifier.

    摘要翻译： 本发明提供一种通过使数据线读出放大器的读和写操作同步来实现高性能随机读/写SDRAM设计的方法和装置。 这使得设计能够执行随机读取和写入操作，而不会改变周期时间问题或不平衡边际问题。 数据线用作双向线路，以最少的附加线路开销实现高性能读写。 在读取操作期间，将读取数据从设备的存储器单元跨越一系列连续的数据线对传送到存储器件的输入/输出端口。 第一对数据线耦合到数据线读出放大器。 附加的数据线对耦合到附加的放大器。 在读取操作期间，根据相应放大器的定时周期，在连续的数据线对之间传送数据。 为了在写入操作期间快速驱动数据信号，连续的一连串数据线对，除了第一对数据线之外的每对数据线的定时信号被禁用，使得数据线被允许 浮动，然后数据线与写入数据过载，使得写入数据快速地将数据线系列快速转换到所选择的数据线读出放大器，其中它大约在读取数据在定时期间正常到达的时间到达 周期为数据线读出放大器。

    Semiconductor memory device with improved read signal generation of data lines and assisted precharge to mid-level
    7.
    发明授权
    Semiconductor memory device with improved read signal generation of data lines and assisted precharge to mid-level 失效
    半导体存储器件具有改进的数据线读信号生成和辅助预充电到中级

    公开(公告)号：US5796665A

    公开(公告)日：1998-08-18

    申请号：US958205

    申请日：1997-10-17

    申请人： Luigi Ternullo, Jr. ,  Michael C. Stephens, Jr.

    发明人： Luigi Ternullo, Jr. ,  Michael C. Stephens, Jr.

    IPC分类号： G11C7/10 ,  G11C13/00

    CPC分类号： G11C7/1078 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/1051

    摘要： A semiconductor memory device with a pair of data lines for reading and writing data signals to and from a matrix of memory cells and an accelerator circuit for accelerating the generation of a data signal on at least one of the data lines is disclosed. Slow signal generation on the data lines is due to the characteristics of NFET pass gates passing high signals, or PFET pass gates passing low signals. In an implementation using NFET pass gates, the accelerator circuit includes a pair of cross-coupled PFET transistors, one of which is activated by the low signal on the opposing data line. The drains of the cross-coupled PFET transistors are coupled to the data lines, such that when the low signal on the opposing data line activates one of the PFETs, it supplies additional current to the data line receiving the high signal, so as to accelerate the generation of the high signal on the data line. Faster signal generation allows for the data line latches of the circuit to be set earlier, thus allowing the read cycle of the memory device to be faster. An additional result of the increased signal generation on the data line that is receiving a high signal is that at the end of the cycle when the two data lines are coupled together, their average voltage due to charge sharing tends to be closer to a desired midlevel voltage such that less power is required to bring the two data lines to the desired mid-level voltage at the end of the signal cycle.

    摘要翻译： 公开了一种半导体存储器件，其具有用于将数据信号读入和写入存储器单元矩阵的一对数据线，以及用于加速至少一条数据线上的数据信号的产生的加速器电路。 数据线上的慢信号产生是由于NFET通过栅极通过高信号的特性，或PFET通过门通过低信号。 在使用NFET通过门的实现中，加速器电路包括一对交叉耦合的PFET晶体管，其中之一由相对数据线上的低信号激活。 交叉耦合PFET晶体管的漏极耦合到数据线，使得当相对数据线上的低信号激活PFET之一时，它向接收高信号的数据线提供附加电流，以便加速 在数据线上产生高信号。 更快的信号产生允许更早地设置电路的数据线锁存器，从而允许存储器件的读取周期更快。 在接收高信号的数据线上增加的信号产生的附加结果是在两个数据线耦合在一起的周期结束时，由于电荷共享而导致的它们的平均电压倾向于更接近于期望的中间级 电压，使得在信号周期结束时需要更少的功率来使两条数据线达到期望的中间电平电压。

    Timing control circuit for synchronous static random access memory
    8.
    发明授权
    Timing control circuit for synchronous static random access memory 失效
    同步静态随机存取存储器定时控制电路

    公开(公告)号：US5559752A

    公开(公告)日：1996-09-24

    申请号：US514693

    申请日：1995-08-14

    申请人： Michael C. Stephens, Jr. ,  Chitranjan N. Reddy ,  Kenneth A. Poteet

    发明人： Michael C. Stephens, Jr. ,  Chitranjan N. Reddy ,  Kenneth A. Poteet

    IPC分类号： G11C7/22 ,  G11C8/00

    CPC分类号： G11C7/22

    摘要： A timing control circuit (10) is disclosed that provides a timing circuit (12) for controlling the operation of an I/O path circuit (14) in a synchronous static random access memory (SRAM). In a read or write operation, the timing circuit (12) sequentially disables bit line equalization circuits (34), enables sense amplifiers (38), disables I/O line equalization circuits (42), and enables secondary sense amplifiers (44). Further, the timing control (12) initiates a reset operation prior to the completion of the read or write operation. The reset operation includes sequentially enabling the bit line equalization circuits (34), disabling the sense amplifiers (38), enabling the I/O line equalization circuits (42), and disabling the secondary sense amplifiers (44). The timing circuit (12) includes first, second and third delay circuits (20, 22, and 24) to allow for minimum split times for bit line pairs (32) and I/O line pairs (40), and minimum secondary sense amplifier (44) sensing times.

    摘要翻译： 公开了一种定时控制电路（10），其提供用于控制同步静态随机存取存储器（SRAM）中的I / O路径电路（14）的操作的定时电路（12）。 在读或写操作中，定时电路（12）顺序地禁用位线均衡电路（34），使能读出放大器（38），禁止I / O线路均衡电路（42），并使能次级读出放大器（44）。 此外，定时控制（12）在完成读或写操作之前启动复位操作。 复位操作包括顺序启用位线均衡电路（34），禁用读出放大器（38），使能I / O线均衡电路（42），以及禁用次级读出放大器（44）。 定时电路（12）包括第一，第二和第三延迟电路（20,22和24），以允许位线对（32）和I / O线对（40）的最小分割时间和最小次级读出放大器 （44）感应时间。