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    Buried Isolation Layer
    1.
    发明申请
    Buried Isolation Layer 审中-公开
    埋藏隔离层

    公开(公告)号：US20090032885A1

    公开(公告)日：2009-02-05

    申请号：US11877166

    申请日：2007-10-23

    申请人： Michael Church

    发明人： Michael Church

    IPC分类号： H01L29/78 ,  H01L29/00

    CPC分类号： H01L21/761 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/167 ,  H01L29/7322 ,  H01L29/7816

    摘要： The present disclosed integrated circuit includes a substrate having a top surface, a buried N type layer in the substrate, N type contact region extending from the surface to the buried N type region, a buried P type region abutting and above the buried N type region in the substrate, a P type contact region extending from the surface to the buried P type region, and an N type device region in the surface and above the buried P type region. The P type impurity of the buried P type region including an impurity of a lower coefficient of diffusion than the coefficient of diffusion of the impurities of the P type contact region.

    摘要翻译： 本公开的集成电路包括：具有上表面的衬底，衬底中的掩埋N型层，从表面延伸到掩埋N型区的N型接触区，与掩埋N型区相邻并且高于掩埋N型区的掩埋P型区 在基板中，从表面延伸到掩埋P型区域的P型接触区域，以及表面上和掩埋P型区域上方的N型器件区域。 掩埋P型区域的P型杂质包含比P型接触区域的杂质扩散系数低的扩散系数的杂质。

    Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general-purpose CMOS technology with thick gate oxide
    2.
    发明申请
    Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general-purpose CMOS technology with thick gate oxide 失效
    多时间可编程（MTP）PMOS浮动栅极非易失性存储器件，用于具有厚栅极氧化物的通用CMOS技术

    公开(公告)号：US20070121381A1

    公开(公告)日：2007-05-31

    申请号：US11508771

    申请日：2006-08-23

    申请人： Alexander Kalnitsky ,  Michael Church

    发明人： Alexander Kalnitsky ,  Michael Church

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0433 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

    摘要： A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.

    摘要翻译： 根据实施例的多时间可编程（MTP）存储单元包括浮置栅极PMOS晶体管，高电压NMOS晶体管和n阱电容器。 浮置栅极PMOS晶体管包括形成存储单元的第一端子，漏极和栅极的源极。 高电压NMOS晶体管包括连接到地的源极，连接到PMOS晶体管的漏极的延伸漏极和形成存储器单元的第二端子的栅极。 n阱电容器包括连接到PMOS晶体管的栅极的第一端子和形成存储器单元的第三端子的第二端子。 浮置栅极PMOS晶体管可以存储逻辑状态。 可以将组合的电压施加到存储单元的第一，第二和第三端子，以编程，禁止程序，读取和擦除逻辑状态。

    ESD structure
    4.
    发明申请
    ESD structure 有权
    ESD结构

    公开(公告)号：US20060097293A1

    公开(公告)日：2006-05-11

    申请号：US11267175

    申请日：2005-11-07

    申请人： Stephen Gaul ,  Michael Church ,  James Vinson

    发明人： Stephen Gaul ,  Michael Church ,  James Vinson

    IPC分类号： H01L29/76

    CPC分类号： H01L29/78 ,  H01L27/0251

    摘要： An IGFET that minimizes the effect of the dislocation at the edge of the device region by displacing the lateral edges of the source and drain regions from the adjacent edge of the opening and the dislocation. This minimizes the lateral diffusion of the source and drain impurities and the formation of metal silicides into the dislocation region. The spacing of the lateral edges of the source and drain regions from the adjacent edge of the opening and the dislocation region is produced by providing additional lateral opposed second gate regions or oxide barrier layer extending from the oxide layer into the adjacent regions of the substrate region and the first gate region extending therebetween. Both the first gate region and the two second gate regions or barrier layer are used in the self-aligned processing of the source and drain regions. The first gate region defines the length of the channel, while the two opposed second gate regions or barrier layer define the width of the channel region. The second gate portion or barrier extends sufficiently into the substrate region to space the width of the channel from the adjacent edge of the opening in the oxide.

    摘要翻译： IGFET，其通过从源极和漏极区域的相邻边缘和位错移位源极和漏极区域的侧边缘来最小化器件区域边缘处位错的影响。 这使源极和漏极杂质的横向扩散和金属硅化物形成到位错区域最小化。 源极和漏极区域与开口的相邻边缘和位错区域的横向边缘的间隔通过提供从氧化物层延伸到衬底区域的相邻区域中的附加横向相对的第二栅极区域或氧化物阻挡层而产生 并且其间延伸的第一栅极区域。 在源极和漏极区域的自对准处理中都使用第一栅极区域和两个第二栅极区域或势垒层。 第一栅极区域限定沟道的长度，而两个相对的第二栅极区域或阻挡层限定沟道区域的宽度。 第二栅极部分或屏障充分延伸到衬底区域中，以使通道的宽度与氧化物中的开口的相邻边缘相隔离。

    Method of Forming The NDMOS Device Body With The Reduced Number of Masks
    5.
    发明申请
    Method of Forming The NDMOS Device Body With The Reduced Number of Masks 失效
    形成具有减少掩模数量的NDMOS器件主体的方法

    公开(公告)号：US20090035910A1

    公开(公告)日：2009-02-05

    申请号：US11870794

    申请日：2007-10-11

    申请人： Michael Church

    发明人： Michael Church

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7835 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/167 ,  H01L29/66659

    摘要： This disclosure describes an improved process and resulting structure that allows a single masking step to be used to define both the body and the threshold adjustment layer of the body. The method consists of forming a first mask on a surface of a substrate with an opening exposing a first region of the substrate; implanting through the opening a first impurity of a first conductivity type and having a first diffusion coefficient; and implanting through the opening a second impurity of the first conductivity type and having a second diffusion coefficient lower than the first diffusion coefficient. The first and second impurities are then co-diffused to form a body region of a field effect transistor. The remainder of the device is formed.

    摘要翻译： 本公开描述了改进的过程和结果，其允许使用单个掩蔽步骤来限定身体的身体和阈值调节层。 该方法包括在衬底的表面上形成第一掩模，其中开口暴露衬底的第一区域; 通过所述开口注入具有第一扩散系数的第一导电类型的第一杂质; 以及通过所述开口注入所述第一导电类型的第二杂质，并具有低于所述第一扩散系数的第二扩散系数。 然后将第一和第二杂质共扩散以形成场效应晶体管的体区。 器件的其余部分形成。

    MULTIPLE TIME PROGRAMMABLE (MTP) PMOS FLOATING GATE-BASED NON-VOLATILE MEMORY DEVICE FOR A GENERAL PURPOSE CMOS TECHNOLOGY WITH THICK GATE OXIDE
    7.
    发明申请
    MULTIPLE TIME PROGRAMMABLE (MTP) PMOS FLOATING GATE-BASED NON-VOLATILE MEMORY DEVICE FOR A GENERAL PURPOSE CMOS TECHNOLOGY WITH THICK GATE OXIDE 有权
    多通道时间可编程（MTP）PMOS浮动栅基非易失性存储器件用于一般用途CMOS技术与厚栅氧化物

    公开(公告)号：US20110176368A1

    公开(公告)日：2011-07-21

    申请号：US13077065

    申请日：2011-03-31

    申请人： Alexander Kalnitsky ,  Michael Church

    发明人： Alexander Kalnitsky ,  Michael Church

    IPC分类号： G11C16/04 ,  H01L29/94

    CPC分类号： G11C16/0433 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

    摘要： A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.

    摘要翻译： 根据实施例的多时间可编程（MTP）存储单元包括浮置栅极PMOS晶体管，高电压NMOS晶体管和n阱电容器。 浮置栅极PMOS晶体管包括形成存储单元的第一端子，漏极和栅极的源极。 高电压NMOS晶体管包括连接到地的源极，连接到PMOS晶体管的漏极的扩展漏极和形成存储器单元的第二端子的栅极。 n阱电容器包括连接到PMOS晶体管的栅极的第一端子和形成存储器单元的第三端子的第二端子。 浮置栅极PMOS晶体管可以存储逻辑状态。 可以将组合的电压施加到存储单元的第一，第二和第三端子，以编程，禁止程序，读取和擦除逻辑状态。

    MULTIPLE TIME PROGRAMMABLE (MTP) PMOS FLOATING GATE-BASED NON-VOLATILE MEMORY DEVICE FOR A GENERAL PURPOSE CMOS TECHNOLOGY WITH THICK GATE OXIDE
    10.
    发明申请
    MULTIPLE TIME PROGRAMMABLE (MTP) PMOS FLOATING GATE-BASED NON-VOLATILE MEMORY DEVICE FOR A GENERAL PURPOSE CMOS TECHNOLOGY WITH THICK GATE OXIDE 有权
    多通道时间可编程（MTP）PMOS浮动栅基非易失性存储器件用于一般用途CMOS技术与厚栅氧化物

    公开(公告)号：US20090207655A1

    公开(公告)日：2009-08-20

    申请号：US12430007

    申请日：2009-04-24

    申请人： Alexander Kalnitsky ,  Michael Church

    发明人： Alexander Kalnitsky ,  Michael Church

    IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C11/34

    CPC分类号： G11C16/0433 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

    摘要： A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.

    摘要翻译： 根据实施例的多时间可编程（MTP）存储单元包括浮置栅极PMOS晶体管，高电压NMOS晶体管和n阱电容器。 浮置栅极PMOS晶体管包括形成存储单元的第一端子，漏极和栅极的源极。 高电压NMOS晶体管包括连接到地的源极，连接到PMOS晶体管的漏极的延伸漏极和形成存储器单元的第二端子的栅极。 n阱电容器包括连接到PMOS晶体管的栅极的第一端子和形成存储器单元的第三端子的第二端子。 浮置栅极PMOS晶体管可以存储逻辑状态。 可以将组合的电压施加到存储单元的第一，第二和第三端子，以编程，禁止程序，读取和擦除逻辑状态。