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1.发明授权DIMM connector accomodating sideband signals for battery status and/or control 有权DIMM连接器，用于容纳用于电池状态和/或控制的边带信号公开(公告)号：US07007184B2
公开(公告)日：2006-02-28
申请号：US09948890
申请日：2001-09-07
IPC分类号： H01M10/46
CPC分类号： G11C5/141 , G06F13/4022 , G11C5/14
摘要： A DIMM connector, including pins for transmitting side band signals for at least one of battery status or control for a battery backed cache is disclosed.
摘要翻译： 公开了一种DIMM连接器，其包括用于发送用于电池状态或电池保护的高速缓存的控制中的至少一个的边带信号的引脚。
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公开(公告)号：US07793089B2
公开(公告)日：2010-09-07
申请号：US11669839
申请日：2007-01-31
CPC分类号： G06F13/409 , G06F13/4022
摘要： A method comprises obtaining connectivity information from a plurality of electrical devices. Each such electrical device is separately coupled to a backplane, and at least one electrical device comprises a plurality of electrical interfaces adapted to be selectively coupled to each of multiple other electrical devices. Based on connectivity information from the at least one electrical device, the method further comprises providing configuration information to the at least one electrical device to cause the at least one electrical device to electrically couple to a target other electrical device via the backplane.
摘要翻译： 一种方法包括从多个电气设备获得连接信息。 每个这样的电气设备单独耦合到背板，并且至少一个电气设备包括适于选择性地耦合到多个其他电气设备中的每一个的多个电接口。 基于来自至少一个电气设备的连接信息，所述方法还包括向所述至少一个电气设备提供配置信息以使所述至少一个电气设备经由所述背板电耦合到目标其他电气设备。
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3.发明授权Peripheral controller comprising first messaging unit for communication with first OS driver and second messaging unit for communication with second OS driver for mass-storage peripheral 失效外围控制器包括用于与第一OS驱动器通信的第一消息单元和用于与用于大容量存储外设的第二OS驱动器通信的第二消息单元
公开(公告)号：US6154789A
公开(公告)日：2000-11-28
申请号：US97409
申请日：1998-06-15
CPC分类号： G06F13/385 , G06F13/102
摘要： An embodiment of the present invention provides a peripheral controller for coupling a mass storage peripheral to a computer system. In a disclosed embodiment the peripheral controller is a disk array controller programmed for RAID. The peripheral controller includes a first messaging unit (FMU), a second messaging unit (SMU), and a peripheral interface which are connected by a local bus. The FMU responds to messages from a first operating system driver. The SMU responds to messages from a different second operating system driver. In one embodiment, the FMU responds to commands from the first operating system driver which is non-standard. In another embodiment, the SMU responds to commands from the second operating system driver which is compatible with the I2O standard. In the disclosed embodiment, the peripheral interface controls mass storage peripherals in response to messages sent to the FMU or the SMU.
摘要翻译： 本发明的实施例提供了一种用于将大容量存储外围设备耦合到计算机系统的外围控制器。 在公开的实施例中，外围控制器是针对RAID编程的盘阵列控制器。 外围控制器包括通过本地总线连接的第一消息接发单元（FMU），第二通信单元（SMU）和外围接口。 FMU响应来自第一个操作系统驱动程序的消息。 SMU响应来自不同第二操作系统驱动程序的消息。 在一个实施例中，FMU响应来自非标准的第一操作系统驱动器的命令。 在另一实施例中，SMU响应来自与I2O标准兼容的第二操作系统驱动器的命令。 在所公开的实施例中，外围接口响应于发送到FMU或SMU的消息来控制大容量存储外设。
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4.发明授权System and method for sending data across a bus cable having in-band and side-band signal conductors 有权通过具有带内和边带信号导体的总线电缆发送数据的系统和方法公开(公告)号：US07506085B2
公开(公告)日：2009-03-17
申请号：US11551438
申请日：2006-10-20
CPC分类号： G06F13/387 , H04L7/0008
摘要： A method and apparatus for sending data. One exemplary embodiment may be a method comprising sending a data rate synchronization pulse from drive controller in a computer system to a storage device controller, calculating a bit transfer period by the storage device controller based on the time duration of the data rate synchronization pulse, serially driving a plurality of bits from the drive controller at a rate based on the bit transfer period, and sampling at the rate based on the bit transfer period to receive the plurality of bits by the storage device controller.
摘要翻译： 一种用于发送数据的方法和装置。 一个示例性实施例可以是一种方法，包括从计算机系统中的驱动控制器向存储设备控制器发送数据速率同步脉冲，基于数据速率同步脉冲的持续时间，由存储设备控制器计算位传输周期 以驱动控制器为基础，以比特传输周期的速率驱动多个比特，并根据比特传送周期以该速率进行采样，由存储装置控制器接收多个比特。
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公开(公告)号：US20080183906A1
公开(公告)日：2008-07-31
申请号：US11669839
申请日：2007-01-31
IPC分类号： G06F13/10
CPC分类号： G06F13/409 , G06F13/4022
摘要： A method comprises obtaining connectivity information from a plurality of electrical devices. Each such electrical device is separately coupled to a backplane, and at least one electrical device comprises a plurality of electrical interfaces adapted to be selectively coupled to each of multiple other electrical devices. Based on connectivity information from the at least one electrical device, the method further comprises providing configuration information to the at least one electrical device to cause the at least one electrical device to electrically couple to a target other electrical device via the backplane.
摘要翻译： 一种方法包括从多个电气设备获得连接信息。 每个这样的电气设备单独耦合到背板，并且至少一个电气设备包括适于选择性地耦合到多个其他电气设备中的每一个的多个电接口。 基于来自至少一个电气设备的连接信息，所述方法还包括向所述至少一个电气设备提供配置信息以使所述至少一个电气设备经由所述背板电耦合到目标其他电气设备。
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6.发明授权System and method for electrically isolating a device from higher voltage devices 失效将器件与较高电压器件电隔离的系统和方法公开(公告)号：US06205500B1
公开(公告)日：2001-03-20
申请号：US08936208
申请日：1997-09-24
IPC分类号： G06I1300
CPC分类号： G06F13/4068 , Y10T307/675
摘要： An isolation system and method that electrically couples a device to a bus during cycles associated with or accessing the device, but otherwise isolates the device from the bus. The isolation system includes an isolation device coupled to the device and to the bus that includes an enable input adapted to receive an enable signal, where the isolation device electrically couples the device to said bus while the enable signal is asserted, but otherwise electrically isolates the device from the bus. The isolation system further includes enable logic that detects cycles on the bus and provides the enable signal to the enable input of the isolation device during a cycle if the cycle is associated with the device. The isolation device may comprise a bus switch, one or more discrete isolating devices such as bipolar transistors, field-effect transistors, or any other suitable device for isolating a device from the bus. Generally, the enable logic may comprise decode logic that decodes an address on the bus during the bus cycle to determine if the address corresponds to an address of the device. Decode logic is usefuil for decoding a memory cycle on the bus for accessing a low voltage memory device, which is otherwise isolated from the bus.
摘要翻译： 一种隔离系统和方法，在与设备相关联或访问设备的周期期间将设备电耦合到总线，但是将设备与总线隔离。 隔离系统包括耦合到装置和总线的隔离装置，该隔离装置包括适于接收使能信号的使能输入，其中隔离装置在使能信号被断言时将该装置电耦合到所述总线，而另外电隔离 设备从公共汽车。 隔离系统还包括启用逻辑，其检测总线上的周期，并且如果周期与设备相关联，则在一个周期期间将启用信号提供给隔离设备的使能输入。 隔离装置可以包括总线开关，一个或多个离散隔离装置，例如双极晶体管，场效应晶体管或用于将装置与总线隔离的任何其它合适的装置。 通常，使能逻辑可以包括在总线周期期间解码总线上的地址以确定地址是否对应于设备的地址的解码逻辑。 解码逻辑是用于解码总线上的存储器周期的用途，用于访问与总线隔离的低电压存储器件。
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7.发明授权System and method for sending data at sampling rate based on bit transfer period 失效基于位传输周期以采样率发送数据的系统和方法公开(公告)号：US07149825B2
公开(公告)日：2006-12-12
申请号：US10637286
申请日：2003-08-08
CPC分类号： G06F13/387 , H04L7/0008
摘要： A method and apparatus for sending data. One exemplary embodiment may be a method comprising sending a data rate synchronization pulse from drive controller in a computer system to a storage device controller, calculating a bit transfer period by the storage device controller based on the time duration of the data rate synchronization pulse, serially driving a plurality of bits from the drive controller at a rate based on the bit transfer period, and sampling at the rate based on the bit transfer period to receive the plurality of bits by the storage device controller.
摘要翻译： 一种用于发送数据的方法和装置。 一个示例性实施例可以是一种方法，包括从计算机系统中的驱动控制器向存储设备控制器发送数据速率同步脉冲，基于数据速率同步脉冲的持续时间，由存储设备控制器计算位传输周期 以驱动控制器为基础，以比特传输周期的速率驱动多个比特，并根据比特传送周期以该速率进行采样，由存储装置控制器接收多个比特。
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8.发明授权Electronic apparatus having I/O board with cable-free redundant adapter cards thereon 失效具有I / O板的电子设备，其上具有无电缆冗余适配器卡
公开(公告)号：US5986880A
公开(公告)日：1999-11-16
申请号：US876730
申请日：1997-06-16
CPC分类号： G06F13/409
摘要： The cage-supported hard disk drives in a computer server system are coupled to connectors on the cage back plane circuit boards and are controlled by a pair of array controller cards which are hot-plug connected in a redundant manner on the system I/O board using a pair of connectors mounted on the I/O board, each connector having first and second sets of electrical contacts thereon. Connector edge portions of the array controller cards are plugged into the I/O board connectors and have first and second sets of electrical contacts that engage the corresponding first and second sets of electrical contacts on their associated I/O board connectors. Formed on the I/O board are (1) a peripheral interconnect bus structure connected to the first sets of connector electrical contacts, (2) an electrical bus structure connected to the second sets of connector electrical contacts and associated cable connectors, and (3) an intercontroller bus structure connected between the second sets of connector electrical contacts and enabling the two array controller cards to communicate with one another independently of the peripheral interconnect bus structure. Electrical cables are interconnected between the electrical bus structure and the back plane circuit boards to couple the array controller cards thereto in a redundant control manner without requiring direct cable connection to either of the array controller cards.
摘要翻译： 计算机服务器系统中的笼式硬盘驱动器耦合到保持架背板电路板上的连接器，并由一对阵列控制器卡控制，这些阵列控制器卡以冗余方式热插拔连接到系统I / O板上 使用安装在I / O板上的一对连接器，每个连接器在其上具有第一组和第二组电触点。 阵列控制器卡的连接器边缘部分插入到I / O板连接器中，并且具有接合在其相关联的I / O板连接器上的对应的第一和第二组电触头的第一组和第二组电触点。 在I / O板上形成有（1）连接到第一组连接器电触点的外围互连总线结构，（2）连接到第二组连接器电触头和相关电缆连接器的电总线结构，和（3 ）连接在所述第二组连接器电触头之间并且使得所述两个阵列控制器卡能够独立于所述外围互连总线结构彼此通信的互连控制器总线结构。 电气电缆在电气总线结构和背板电路板之间互连，以便以冗余控制方式将阵列控制器卡耦合到其上，而不需要直接连接到阵列控制器卡中的任何一个。
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9.发明授权Secondary channel for command information for fibre channel system interface bus 失效光纤通道系统接口总线命令信息的二级通道
公开(公告)号：US5848251A
公开(公告)日：1998-12-08
申请号：US692516
申请日：1996-08-06
CPC分类号： G06F13/4278
摘要： The present invention relates to a secondary channel for a point-to-point burst style bus associated with a computer system. The point-to-point bus may originate as a standardized bus from a fibre channel controller. The point-to-point bus connects to another circuit which may be a bridge circuit, a minicomputer or a peripheral device. A secondary channel is also connected to the point-to-point bus and is adapted to share the bus by receiving information having predetermined addresses. The information recieved by the secondary channel can be stored in a memory that is shared with a processor. Command/control information can be extracted from the point-to-point bus before data is transferred through the bridge circuit in order to allow the data to be acted on more quickly by processing/storage devices since the control data was already made available to the storage devices via the secondary channel.
摘要翻译： 本发明涉及一种与计算机系统相关联的点对点突发样式总线的辅助信道。 点对点总线可以作为来自光纤通道控制器的标准化总线发起。 点对点总线连接到另一个可能是桥接电路，小型计算机或外围设备的电路。 辅助信道也连接到点对点总线，并且适于通过接收具有预定地址的信息来共享总线。 辅助频道接收到的信息可以存储在与处理器共享的存储器中。 在通过桥接电路传输数据之前，可以从点对点总线提取命令/控制信息，以便通过处理/存储设备更快速地执行数据，因为控制数据已经可用于 存储设备通过辅助通道。
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公开(公告)号：US09529395B2
公开(公告)日：2016-12-27
申请号：US14376138
申请日：2012-03-12
申请人： John P. Franz , Michael L. Sabotta , Tahir Cader , David A. Moore
发明人： John P. Franz , Michael L. Sabotta , Tahir Cader , David A. Moore
CPC分类号： G06F1/20 , F28D15/0275 , G06F1/206 , H05K7/20772 , H05K7/20781
摘要： Examples of the present disclosure may include methods and systems for liquid temperature control cooling. An example of a liquid temperature control cooling system for an electronics rack (100, 200a, 200b) can include a number of electronic devices (102, 202) in the electronics rack (100, 200a, 200b), a panel (108-1, 108-2, 208-1, 224-1, 224-2) that extends from a roof (226) to a floor (228) inside the electronics rack (100, 200a, 200b), where a face of the panel (108-1, 108-2, 208-1, 224-1, 224-2) is parallel to a direction in which the number of electronic devices (100, 200a, 200b) slide into the electronics rack (100, 200a, 200b) and perpendicular to a front of the electronics rack, and a heat receiving structure (112, 212, 312, 412) that is integrated into the panel (108-1, 108-2, 208-1, 224-1, 224-2) and that is thermally coupled to the number of electronic devices (102, 202) through the panel (108-1, 108-2, 208-1, 224-1, 224-2), where the heat receiving structure (112, 212, 312, 412) can include a liquid flow compartment (330, 442) an input (216, 316, 416) to receive cool liquid into the liquid flow compartment (330, 442), and a control valve (214, 314, 414-1, 414-2, 414-3, 414-4) to release warm liquid from the liquid flow compartment (330, 442).
摘要翻译： 本公开的实例可以包括用于液体温度控制冷却的方法和系统。 用于电子机架（100,200a，200b）的液体温度控制冷却系统的示例可以包括电子机架（100,200a，200b）中的多个电子设备（102,202），面板（108-1 ，108-2,208-1,224-1,224-2），其从所述电子机架（100,200a，200b）内部的屋顶（226）延伸到地板（228），其中所述面板 108-1,108-2,208-1,224-1,224-2）平行于电子设备（100,200a，200b）的数量滑入电子机架（100,200a，200b）的方向 ）和垂直于所述电子机架的前部的热接收结构（112,212,312,412），其被集成到所述面板（108-1,108-2,208-1,224-1,224-212）中， 2），并且其通过面板（108-1,108-2,208-1,224-1,224-2）热耦合到电子设备（102,202）的数量，其中热接收结构（112） ，212,312,412）可以包括液体流动隔室（330,442），输入端（216,316,416）以将冷却液体接收到 液体流动室（330,442）和用于从液体流动室（330,442）释放温热液体的控制阀（214,314,414-1,414-2,414-3,414-4）。
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