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    Method and apparatus for coherent memory structure of heterogeneous processor systems
    4.
    发明授权
    Method and apparatus for coherent memory structure of heterogeneous processor systems 失效
    异构处理器系统的相干存储器结构的方法和装置

    公开(公告)号：US07093080B2

    公开(公告)日：2006-08-15

    申请号：US10682386

    申请日：2003-10-09

    申请人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle ,  David J. Shippy ,  Thuong Quang Truong

    发明人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle ,  David J. Shippy ,  Thuong Quang Truong

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0835

    摘要： Disclosed is a coherent cache system that operates in conjunction with non-homogeneous processing units. A set of processing units of a first configuration has conventional cache and directly accesses common or shared system physical and virtual address memory through the use of a conventional MMU (Memory Management Unit). Additional processors of a different configuration and/or other devices that need to access system memory are configured to store accessed data in compatible caches. Each of the caches is compatible with a given protocol coherent memory management bus interspersed between the caches and the system memory.

    摘要翻译： 公开了与非均匀处理单元结合操作的一致的缓存系统。 一组第一配置的处理单元具有常规高速缓存，并且通过使用常规MMU（存储器管理单元）直接访问公用或共享系统物理和虚拟地址存储器。 需要访问系统存储器的不同配置和/或其他设备的其他处理器被配置为将访问的数据存储在兼容的高速缓存中。 每个缓存与散列在高速缓存和系统存储器之间的给定协议相干存储器管理总线兼容。

    Software-controlled cache set management
    5.
    发明授权
    Software-controlled cache set management 失效
    软件控制缓存集管理

    公开(公告)号：US07120748B2

    公开(公告)日：2006-10-10

    申请号：US10655367

    申请日：2003-09-04

    申请人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Roy Johns ,  James Allan Kahle ,  David Shippy ,  Thuong Quang Truong ,  Takeshi Yamazaki

    发明人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Roy Johns ,  James Allan Kahle ,  David Shippy ,  Thuong Quang Truong ,  Takeshi Yamazaki

    IPC分类号： G06F12/00

    CPC分类号： G06F12/126

    摘要： The present invention provides a system for managing cache replacement eligibility. A first address register is configured to request an address from an L1 cache. An L1 cache is configured to determine whether a requested address is in the L1 cache and, in response to a determination that a requested address is not in the L1 cache, is further configured to transmit the requested address to a range register coupled to the L1 cache. The range register is configured to generate a class identifier in response to a received requested address and to transmit the requested address and class identifier to a replacement management table coupled to the range register. The replacement management table is configured to generate L2 tag replacement control indicia in response to a received requested address and class identifier. An L2 address register is coupled to the first address register and configured to request an address from an L2 cache. An L2 cache is coupled to the L2 address register and the replacement management table and is configured to determine whether a requested address is in the L2 cache and is further configured to assign replacement eligibility of at least one set of cache lines in the L2 cache in response to received L2 tag replacement control indicia. In response to a determination that a requested address is not in the L2 cache, the L2 cache is further configured to overwrite a cache line within a set of the L2 cache as a function of the replacement eligibility.

    摘要翻译： 本发明提供了一种用于管理高速缓存替换资格的系统。 第一地址寄存器被配置为从L1高速缓存请求地址。 L1缓存被配置为确定所请求的地址是否在L1高速缓存中，并且响应于所请求的地址不在L1高速缓存中的确定，还被配置为将所请求的地址发送到耦合到L1的范围寄存器 缓存。 范围寄存器被配置为响应于接收到的请求的地址生成类标识符，并将所请求的地址和类标识符发送到耦合到范围寄存器的替换管理表。 替换管理表被配置为响应于接收到的请求的地址和类标识符来生成L2标签替换控制标记。 L2地址寄存器耦合到第一地址寄存器并且被配置为从L2高速缓存请求地址。 L2缓存耦合到L2地址寄存器和替换管理表，并且被配置为确定所请求的地址是否在L2高速缓存中，并被进一步配置为在L2高速缓存中分配至少一组高速缓存行的替换资格 响应接收的L2标签替换控制标记。 响应于所请求的地址不在L2高速缓存中的确定，L2高速缓存进一步被配置为根据替换资格来覆盖L2高速缓存中的高速缓存行。

    System for asynchronous DMA command completion notification wherein the DMA command comprising a tag belongs to a plurality of tag groups
    7.
    发明授权
    System for asynchronous DMA command completion notification wherein the DMA command comprising a tag belongs to a plurality of tag groups 失效
    用于异步DMA命令完成通知的系统，其中包括标签的DMA命令属于多个标签组

    公开(公告)号：US07546393B2

    公开(公告)日：2009-06-09

    申请号：US11695436

    申请日：2007-04-02

    申请人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  Peichum Peter Liu ,  Thuong Quang Truong ,  Takeshi Yamazaki

    发明人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  Peichum Peter Liu ,  Thuong Quang Truong ,  Takeshi Yamazaki

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28

    摘要： The present invention provides for a system comprising a DMA queue configured to receive a DMA command comprising a tag, wherein the tag belongs to one of a plurality of tag groups. A counter couples to the DMA queue and is configured to increment a tag group count of the tag group to which the tag belongs upon receipt of the DMA command by the DMA queue and to decrement the tag group count upon execution of the DMA command. A tag group count status register couples to the counter and is configured to store the tag group count for each of the plurality of tag groups. And the tag group count status register is further configured to receive a request for a tag group status and to respond to the request for the tag group status.

    摘要翻译： 本发明提供一种包括配置成接收包括标签的DMA命令的DMA队列的系统，其中标签属于多个标签组之一。 计数器耦合到DMA队列，并配置为在DMA队列接收到DMA命令时增加标签组所属标签组的标签组计数，并在执行DMA命令时递减标签组计数。 标签组计数状态寄存器耦合到计数器，并被配置为存储多个标签组中的每一个的标签组计数。 并且标签组计数状态寄存器被进一步配置为接收对标签组状态的请求并响应对标签组状态的请求。

    Hierarchical management for multiprocessor system with real-time attributes
    8.
    发明授权
    Hierarchical management for multiprocessor system with real-time attributes 失效
    具有实时属性的多处理器系统的分层管理

    公开(公告)号：US07299372B2

    公开(公告)日：2007-11-20

    申请号：US10912481

    申请日：2004-08-05

    申请人： Jeffrey Douglas Brown ,  Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle ,  Michael Fan Wang

    发明人： Jeffrey Douglas Brown ,  Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle ,  Michael Fan Wang

    IPC分类号： G06F1/28

    CPC分类号： G06F1/3203

    摘要： The present invention provides for controlling the power consumption of an element. A first power control command is issued by software for the element. It is determined if the power control command corresponds to an allowable power control state for that element as defined by the hardware. If the power control command is not an allowable power control state for that element, the hardware sets the power control at a higher level than the power control state issued by the software. The software is real time software, and the software also sets minimally acceptable activity control states. A hierarchy of power consumption is defined for different elements of a chip by software, which provides the minimum level of power consumption by any element or sub-element on a chip.

    摘要翻译： 本发明提供用于控制元件的功耗。 第一个功率控制命令由该元件的软件发出。 确定功率控制命令是否对应于由硬件定义的该元件的容许功率控制状态。 如果功率控制命令不是该元件的允许功率控制状态，则硬件将功率控制设置在比由软件发出的功率控制状态更高的水平。 该软件是实时软件，软件还设置了最低限度可接受的活动控制状态。 通过软件为芯片的不同元件定义功耗层级，其通过芯片上的任何元件或子元件提供最低功耗水平。

    Symmetric multiprocessor coherence mechanism
    9.
    发明授权
    Symmetric multiprocessor coherence mechanism 有权
    对称多处理器一致性机制

    公开(公告)号：US06760819B2

    公开(公告)日：2004-07-06

    申请号：US09895888

    申请日：2001-06-29

    申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Charles Ray Johns ,  John Samuel Liberty ,  Thuong Quang Truong

    发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Charles Ray Johns ,  John Samuel Liberty ,  Thuong Quang Truong

    IPC分类号： G06F1208

    CPC分类号： G06F12/0822 ,  G06F12/0811 ,  G06F12/084

    摘要： A processor-cache operational scheme and topology within a multi-processor data processing system having a shared lower level cache (or memory) by which the number of coherency busses is reduced and more efficient snoop resolution and coherency operations with the processor caches are provided. A copy of the internal (L1) cache directory is provided within the lower level (L2) cache or memory. The snoop operations and coherency maintenance operations of the L1 directory are completed by comparing the snoop addresses with the address tags of the copy of the L1 directory in the L2 cache. Updates to the coherency states of the copy of the L1 directory are mirrored in the L1 directory and L1 cache. This eliminates the need for the individual coherency buses of each processor that is coupled to the L2 cache and speeds up coherency operations because the snoops do not have to be transmitted to the L1 caches.

    摘要翻译： 提供具有共享低级高速缓存（或存储器）的多处理器数据处理系统中的处理器 - 高速缓存操作方案和拓扑，通过该共享低级高速缓存（或存储器）减少一致性总线的数量并且提供与处理器高速缓存更有效的窥探分辨率和一致性操作。 在低级（L2）高速缓存或内存中提供内部（L1）缓存目录的副本。 通过将侦听地址与L2缓存中L1目录的副本的地址标签进行比较，完成L1目录的侦听操作和一致性维护操作。 对L1目录的副本的一致性状态的更新被镜像在L1目录和L1缓存中。 这消除了对耦合到L2高速缓存的每个处理器的各个一致性总线的需要，并且加速一致性操作，因为该探测不必被传送到L1高速缓存。

    Computer architecture and software cells for broadband networks
    10.
    发明授权
    Computer architecture and software cells for broadband networks 有权
    宽带网络的计算机架构和软件单元

    公开(公告)号：US07233998B2

    公开(公告)日：2007-06-19

    申请号：US09816004

    申请日：2001-03-22

    申请人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  Charles Ray Johns ,  James Allan Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

    发明人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  Charles Ray Johns ,  James Allan Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

    IPC分类号： G06F15/16

    CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

    摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

    摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。 还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。