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    Method and apparatus for coherent memory structure of heterogeneous processor systems
    4.
    发明授权
    Method and apparatus for coherent memory structure of heterogeneous processor systems 失效
    异构处理器系统的相干存储器结构的方法和装置

    公开(公告)号：US07093080B2

    公开(公告)日：2006-08-15

    申请号：US10682386

    申请日：2003-10-09

    申请人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle ,  David J. Shippy ,  Thuong Quang Truong

    发明人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle ,  David J. Shippy ,  Thuong Quang Truong

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0835

    摘要： Disclosed is a coherent cache system that operates in conjunction with non-homogeneous processing units. A set of processing units of a first configuration has conventional cache and directly accesses common or shared system physical and virtual address memory through the use of a conventional MMU (Memory Management Unit). Additional processors of a different configuration and/or other devices that need to access system memory are configured to store accessed data in compatible caches. Each of the caches is compatible with a given protocol coherent memory management bus interspersed between the caches and the system memory.

    摘要翻译： 公开了与非均匀处理单元结合操作的一致的缓存系统。 一组第一配置的处理单元具有常规高速缓存，并且通过使用常规MMU（存储器管理单元）直接访问公用或共享系统物理和虚拟地址存储器。 需要访问系统存储器的不同配置和/或其他设备的其他处理器被配置为将访问的数据存储在兼容的高速缓存中。 每个缓存与散列在高速缓存和系统存储器之间的给定协议相干存储器管理总线兼容。

    Software-controlled cache set management
    5.
    发明授权
    Software-controlled cache set management 失效
    软件控制缓存集管理

    公开(公告)号：US07120748B2

    公开(公告)日：2006-10-10

    申请号：US10655367

    申请日：2003-09-04

    申请人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Roy Johns ,  James Allan Kahle ,  David Shippy ,  Thuong Quang Truong ,  Takeshi Yamazaki

    发明人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Roy Johns ,  James Allan Kahle ,  David Shippy ,  Thuong Quang Truong ,  Takeshi Yamazaki

    IPC分类号： G06F12/00

    CPC分类号： G06F12/126

    摘要： The present invention provides a system for managing cache replacement eligibility. A first address register is configured to request an address from an L1 cache. An L1 cache is configured to determine whether a requested address is in the L1 cache and, in response to a determination that a requested address is not in the L1 cache, is further configured to transmit the requested address to a range register coupled to the L1 cache. The range register is configured to generate a class identifier in response to a received requested address and to transmit the requested address and class identifier to a replacement management table coupled to the range register. The replacement management table is configured to generate L2 tag replacement control indicia in response to a received requested address and class identifier. An L2 address register is coupled to the first address register and configured to request an address from an L2 cache. An L2 cache is coupled to the L2 address register and the replacement management table and is configured to determine whether a requested address is in the L2 cache and is further configured to assign replacement eligibility of at least one set of cache lines in the L2 cache in response to received L2 tag replacement control indicia. In response to a determination that a requested address is not in the L2 cache, the L2 cache is further configured to overwrite a cache line within a set of the L2 cache as a function of the replacement eligibility.

    摘要翻译： 本发明提供了一种用于管理高速缓存替换资格的系统。 第一地址寄存器被配置为从L1高速缓存请求地址。 L1缓存被配置为确定所请求的地址是否在L1高速缓存中，并且响应于所请求的地址不在L1高速缓存中的确定，还被配置为将所请求的地址发送到耦合到L1的范围寄存器 缓存。 范围寄存器被配置为响应于接收到的请求的地址生成类标识符，并将所请求的地址和类标识符发送到耦合到范围寄存器的替换管理表。 替换管理表被配置为响应于接收到的请求的地址和类标识符来生成L2标签替换控制标记。 L2地址寄存器耦合到第一地址寄存器并且被配置为从L2高速缓存请求地址。 L2缓存耦合到L2地址寄存器和替换管理表，并且被配置为确定所请求的地址是否在L2高速缓存中，并被进一步配置为在L2高速缓存中分配至少一组高速缓存行的替换资格 响应接收的L2标签替换控制标记。 响应于所请求的地址不在L2高速缓存中的确定，L2高速缓存进一步被配置为根据替换资格来覆盖L2高速缓存中的高速缓存行。

    On-chip data transfer in multi-processor system
    6.
    发明授权
    On-chip data transfer in multi-processor system 失效
    多处理器系统中的片上数据传输

    公开(公告)号：US06820143B2

    公开(公告)日：2004-11-16

    申请号：US10322127

    申请日：2002-12-17

    申请人： Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Peichun Peter Liu ,  David Shippy ,  Thuong Quang Truong

    发明人： Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Peichun Peter Liu ,  David Shippy ,  Thuong Quang Truong

    IPC分类号： G06F1328

    CPC分类号： G06F12/0817 ,  G06F12/0897

    摘要： A system and method are provided for improving performance of a computer system by providing a direct data transfer between different processors. The system includes a first and second processor. The first processor is in need of data. The system also includes a directory in communication with the first processor. The directory receives a data request for the data and contains information as to where the data is stored. A cache is coupled to the second processor. An internal bus is coupled between the first processor and the cache to transfer the data from the cache to the first processor when the data is found to be stored in the cache.

    摘要翻译： 提供了一种通过在不同处理器之间提供直接数据传输来提高计算机系统的性能的系统和方法。 该系统包括第一和第二处理器。 第一个处理器需要数据。 该系统还包括与第一处理器通信的目录。 目录接收到数据的数据请求，并包含有关数据存储位置的信息。 缓存耦合到第二处理器。 当发现数据被存储在高速缓存中时，内部总线耦合在第一处理器和高速缓存之间以将数据从高速缓存传送到第一处理器。