公开(公告)号：US07648292B2

公开(公告)日：2010-01-19

申请号：US11831622

申请日：2007-07-31

申请人： Kunie Ogata ,  Koki Nishimuko ,  Hiroshi Tomita ,  Yoshio Kimura ,  Ryouichi Uemura ,  Michio Tanaka

发明人： Kunie Ogata ,  Koki Nishimuko ,  Hiroshi Tomita ,  Yoshio Kimura ,  Ryouichi Uemura ,  Michio Tanaka

IPC分类号： G03D5/00 ,  G03B27/32

摘要： A resist pattern forming method using a coating and developing apparatus and an aligner being connected thereto which are controlled to form a resist film on a surface of a substrate with a base film and a base pattern formed thereon, followed by inspecting at least one of a plurality of measurement items selected from: reflection ratio and film thickness of the base film and the resist film, line width after a development, an accuracy that the base pattern matches with a resist pattern, a defect on the surface after the development, etc. A parameter subject to amendment is selected based on corresponding data of each measurement item, such as the film thickness of the resist and the line width after the development, and amendment of the parameter is performed. This results in a reduced workload of an operator, and the appropriate amendment can be performed.

公开(公告)号：US20090162759A1

公开(公告)日：2009-06-25

申请号：US12065782

申请日：2006-09-13

申请人： Kunie Ogata ,  Hiroshi Tomita ,  Michio Tanaka ,  Ryoichi Uemura

发明人： Kunie Ogata ,  Hiroshi Tomita ,  Michio Tanaka ,  Ryoichi Uemura

IPC分类号： G03C5/00

CPC分类号： H01L21/67225 ,  G03F7/168 ,  G03F7/3071 ,  G03F7/40 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： A pattern forming system 1 includes a checking apparatus 400, a storage device 502, and a control section 500. The checking apparatus 400 is configured to measure and check a state of a resist pattern formed on a substrate W after a developing process and output a first check result thus obtained, and to measure and check a state of a pattern formed on the substrate after an etching process and output a second check result thus obtained. The storage device 502 stores a correlation formula obtained from the first check result and the second check result. The control section 500 is configured to use the correlation formula to obtain a target value of the state of the pattern after the developing process from a target value of the state of the pattern after the etching process, and to use a difference between the target value of the state of the pattern after the developing process and the first check result to set a condition for the first heat process and/or the second heat process.

摘要翻译： 图案形成系统1包括检查装置400，存储装置502和控制部500.检查装置400被配置为测量并检查在显影处理之后形成在基板W上的抗蚀剂图案的状态，并输出 第一检查结果，并且在蚀刻处理之后测量和检查在基板上形成的图案的状态，并输出由此获得的第二检查结果。 存储装置502存储从第一检查结果和第二检查结果获得的相关公式。 控制部500被配置为使用相关公式从蚀刻处理之后的图案的状态的目标值获得显影处理之后的图案的状态的目标值，并且使用目标值 的显影过程之后的图案状态和第一检查结果来设定第一加热处理和/或第二加热处理的条件。

公开(公告)号：US07488127B2

公开(公告)日：2009-02-10

申请号：US11199215

申请日：2005-08-09

申请人： Kunie Ogata ,  Koki Nishimuko ,  Hiroshi Tomita ,  Yoshio Kimura ,  Ryouichi Uemura ,  Michio Tanaka

发明人： Kunie Ogata ,  Koki Nishimuko ,  Hiroshi Tomita ,  Yoshio Kimura ,  Ryouichi Uemura ,  Michio Tanaka

IPC分类号： G03D5/00 ,  G03B13/00 ,  G03B27/32

CPC分类号： H01L21/67253 ,  G03F7/162 ,  G03F7/3021 ,  H01L21/6715

摘要： A resist pattern forming apparatus comprising a controller having a controlling portion that controls a processing of a coating and developing apparatus with a coating unit and a developing unit being provided therewith and an aligner being connected thereto, while an inspecting portion and the like measures at least one of a plurality of measurement items selected from, a reflection ratio and a film thickness of a base film and a resist film, a line width after the development, an accuracy that the base film matches with a resist pattern, a defect after the development, and so on. The measured data is transmitted to the controller. At the controller, a parameter subject to an amendment is selected based on the corresponding data of each of the measurement item such as the film thickness of the resist and the line width after the development, and the amendment of the parameters subject to the amendment is performed. As a result, the amending operation is facilitated by a reduced workload of an operator and in the same time, the appropriate amendment can be performed.

公开(公告)号：US07375831B2

公开(公告)日：2008-05-20

申请号：US11013784

申请日：2004-12-17

申请人： Michio Tanaka ,  Masami Yamashita

发明人： Michio Tanaka ,  Masami Yamashita

IPC分类号： G01B11/02

CPC分类号： G03F7/705 ,  G03F7/70625

摘要： In optical line width measurement performed using the scatterometry technique, the present invention measures the line width formed on a substrate more accurately than in the prior art. After a predetermined pattern is formed in a resist film on a substrate, the refractive index and the extinction coefficient of the resist film are measured. Based on the measured values, calculation is performed to obtain calculated light intensity distributions of reflected light reflected from a plurality of virtual patterns. The calculated light intensity distributions are stored, and their library is created. The substrate for which the refractive index and so on are measured is irradiated with light, and the light intensity distribution of its reflected light is measured. The light intensity distribution is collated with the calculated light intensity distributions in the library, so that the line width of the virtual pattern having a matching light intensity distribution is regarded as the line width of the real pattern. Since the library of the light intensity distributions of the virtual pattern is created based on the actually measured refractive index and so on after the formation of the pattern, an accurate line width matching the pattern state at the time of measuring the line width is measured.

摘要翻译： 在使用散射测量技术进行的光线宽度测量中，本发明比现有技术更准确地测量在衬底上形成的线宽。 在基板上的抗蚀剂膜中形成预定图案之后，测量抗蚀剂膜的折射率和消光系数。 基于测量值，执行计算以获得从多个虚拟图案反射的反射光的计算的光强度分布。 存储计算的光强度分布，并创建它们的库。 用光照射测定折射率等的基板，测定其反射光的光强度分布。 将光强度分布与库中计算的光强度分布进行比较，使得具有匹配的光强度分布的虚拟图案的线宽被视为实曲线的线宽。 由于在形成图案之后，基于实际测量的折射率等创建虚拟图案的光强度分布的库，因此测量与测量线宽度时的图案状态匹配的精确线宽。

公开(公告)号：US20060199090A1

公开(公告)日：2006-09-07

申请号：US11362126

申请日：2006-02-27

申请人： Michio Tanaka ,  Masahide Tadokoro

发明人： Michio Tanaka ,  Masahide Tadokoro

IPC分类号： G03B27/00 ,  G03C5/00

CPC分类号： G03F7/70641 ,  Y10S430/136

摘要： In the present invention, in the photolithography process in which a certain focus condition has been already set, a film on a substrate is exposed to only zero-order light of a light source transmitted, and then developed to reduce a first portion of the film on the substrate. Further, the film on the substrate is exposed to zero-order light and higher order light of the light source transmitted, and then developed to reduce a second portion of the film on the substrate. Thereafter, the film thicknesses of the first portion and the second portion are measured, and the measured film thicknesses of the first portion and the second portion are converted into line widths of a resist pattern by previously obtained correlations between the film thicknesses and the line widths. The converted line width of the second portion is then subtracted from the converted line width of the first portion, whereby the line width depending only on the focus component is calculated. Based on the line width, a new focus condition is set.

摘要翻译： 在本发明中，在已经设定了一定的聚焦条件的光刻工艺中，基板上的膜仅暴露于透过的光源的零级光，然后显影以减小膜的第一部分 在基板上。 此外，将基板上的膜暴露于光源的零级光和较高阶光，然后显影以减少基板上的膜的第二部分。 此后，测量第一部分和第二部分的膜厚度，并且通过预先获得的膜厚度和线宽度之间的相关性，将测量的第一部分和第二部分的膜厚度转换为抗蚀剂图案的线宽度 。 然后从第一部分的转换线宽中减去第二部分的转换线宽，由此计算仅依赖于聚焦分量的线宽。 根据线宽，设置新的对焦条件。

公开(公告)号：US20050271382A1

公开(公告)日：2005-12-08

申请号：US11199215

申请日：2005-08-09

申请人： Kunie Ogata ,  Koki Nishimuko ,  Hiroshi Tomita ,  Yoshio Kimura ,  Ryouichi Uemura ,  Michio Tanaka

发明人： Kunie Ogata ,  Koki Nishimuko ,  Hiroshi Tomita ,  Yoshio Kimura ,  Ryouichi Uemura ,  Michio Tanaka

IPC分类号： G03F7/16 ,  B05C11/00 ,  B05C11/08 ,  B05D1/40 ,  B05D3/00 ,  G03F7/20 ,  G03F7/30 ,  H01L21/00 ,  H01L21/027 ,  G03C5/00

CPC分类号： H01L21/67253 ,  G03F7/162 ,  G03F7/3021 ,  H01L21/6715

摘要： A resist pattern forming apparatus comprising a controller having a controlling portion that controls a processing of a coating and developing apparatus with a coating unit and a developing unit being provided therewith and an aligner being connected thereto, while an inspecting portion and the like measures at least one of a plurality of measurement items selected from, a reflection ratio and a film thickness of a base film and a resist film, a line width after the development, an accuracy that the base film matches with a resist pattern, a defect after the development, and so on. The measured data is transmitted to the controller. At the controller, a parameter subject to an amendment is selected based on the corresponding data of each of the measurement item such as the film thickness of the resist and the line width after the development, and the amendment of the parameters subject to the amendment is performed. As a result, the amending operation is facilitated by a reduced workload of an operator and in the same time, the appropriate amendment can be performed.

摘要翻译： 一种抗蚀剂图形形成装置，包括具有控制部分的控制器，所述控制部分控制具有涂覆单元和显影单元的涂布和显影装置的处理，并且与其连接的对准器，同时检查部分等至少测量 选自多个测量项目中的一个，基膜和抗蚀剂膜的反射率和膜厚度，显影后的线宽度，底膜与抗蚀剂图案匹配的精度，显影后的缺陷 ， 等等。 测量的数据被传送到控制器。 控制器根据抗蚀剂的膜厚度和开发后的线宽度等测量项目的对应数据选择修改参数，修改后的参数修改为 执行。 因此，通过减少操作者的工作量来促进修改操作，并且同时可以执行适当的修改。

公开(公告)号：US20050038618A1

公开(公告)日：2005-02-17

申请号：US10494524

申请日：2002-11-13

申请人： Michio Tanaka ,  Makoto Kiyota ,  Takashi Aiuchi ,  Ryouichi Uemura

发明人： Michio Tanaka ,  Makoto Kiyota ,  Takashi Aiuchi ,  Ryouichi Uemura

IPC分类号： G01N21/86 ,  G01N21/956 ,  G03F7/20 ,  H01L21/027 ,  H01L21/66 ,  H01L23/544 ,  G06F19/00

CPC分类号： G03F7/70491 ,  G01N21/95607 ,  G03F7/70625 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： When a base film of a substrate is formed, for instance, on a scribe line of a wafer, a quadrangular first inspection pattern is formed in advance, and when a resist pattern is formed, a second inspection pattern are formed so as to be on a straight line to the first inspection pattern in a top plan view. When light is irradiated to a region including the first inspection pattern and the second inspection pattern and a spectrum is formed based on the reflected diffracted light, information of a line width of the second inspection pattern and a pitch of both inspection patterns is contained therein. In this connection, by preparing in advance a group of spectra based on various kinds of inspection patterns according to simulation and by comparing with an actual spectrum, the most approximate spectrum is selected, and thereby the line width and the pitch are estimated to evaluate the resist pattern.

公开(公告)号：USD471528S1

公开(公告)日：2003-03-11

申请号：US29154422

申请日：2002-01-23

申请人： Kousaku Wada ,  Michio Tanaka

设计人： Kousaku Wada ,  Michio Tanaka

公开(公告)号：US5937290A

公开(公告)日：1999-08-10

申请号：US862992

申请日：1997-05-27

申请人： Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Keizo Kawakita ,  Katsuo Yuhara ,  Kazuhiko Saito ,  Shinya Nishio ,  Michio Tanaka ,  Michio Nishimura ,  Toshiyuki Kaeriyama ,  Songsu Cho

发明人： Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Keizo Kawakita ,  Katsuo Yuhara ,  Kazuhiko Saito ,  Shinya Nishio ,  Michio Tanaka ,  Michio Nishimura ,  Toshiyuki Kaeriyama ,  Songsu Cho

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  Y10S438/942

摘要： In an embodiment of a method of manufacturing semiconductor integrated circuit devices according to the present invention, word lines are provided in a straight form, which serve as gate electrodes of two selecting MOSFETs formed symmetrical about a center portion of an active region surrounded by a LOCOS oxide film on a semiconductor substrate, and bit lines have straight segments and protruding segments. Each protruding segment is formed to protrude from the bit line and is connected through a first contact hole to a first semiconductor region formed at the center portion of the active region. The straight line segments and the protruding segments are formed separately by two separate exposure steps.

摘要翻译： 在根据本发明的制造半导体集成电路器件的方法的实施例中，字线被提供成直线形式，其用作两个选择MOSFET的栅电极，所述选择MOSFET形成为由LOCOS包围的有源区域的中心部分对称地形成 半导体衬底上的氧化膜，位线具有直段和突出段。 每个突出部分形成为从位线突出，并且通过第一接触孔连接到形成在有源区域的中心部分处的第一半导体区域。 直线段和突出段通过两个单独的曝光步骤分别形成。

公开(公告)号：US5578849A

公开(公告)日：1996-11-26

申请号：US341966

申请日：1994-11-16

申请人： Yoshitaka Tadaki ,  Jun Murata ,  Toshihiro Sekiguchi ,  Hideo Aoki ,  Keizo Kawakita ,  Hiroyuki Uchiyama ,  Michio Nishimura ,  Michio Tanaka ,  Yuji Ezaki ,  Kazuhiko Saitoh ,  Katsuo Yuhara ,  Songsu Cho

发明人： Yoshitaka Tadaki ,  Jun Murata ,  Toshihiro Sekiguchi ,  Hideo Aoki ,  Keizo Kawakita ,  Hiroyuki Uchiyama ,  Michio Nishimura ,  Michio Tanaka ,  Yuji Ezaki ,  Kazuhiko Saitoh ,  Katsuo Yuhara ,  Songsu Cho

IPC分类号： H01L21/3205 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/10 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L2924/0002

摘要： A memory device has a semiconductor substrate, and memory cells provided at intersections between word line conductors and bit line conductors. Each memory cell has a switching transistor and an information storage capacitor. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors. A series of memory cell pair unit structures formed under one bit line conductor is positionally shifted with respect to a series of memory cell pair unit structures formed under adjacent first and second bit line conductors on opposite sides of the one bit line conductor, respectively, such that a second information storage capacitor of a memory cell pair unit structure formed under the adjacent first bit line conductor and a first information storage capacitor of a memory cell pair unit structure formed under the adjacent second bit line conductor are located adjacent to a bit line connection conductor of a memory cell pair unit structure formed under the one bit line conductor.

摘要翻译： 存储器件具有半导体衬底和设置在字线导体和位线导体之间的交叉点处的存储单元。 每个存储单元具有开关晶体管和信息存储电容器。 每个位线导体的相邻的两个存储单元形成存储单元对单元结构，其中相邻两个存储单元的晶体管的第一半导体区域在其边界处被结合成单个区域并连接到位线导体之一 通过位线连接导体，相邻的两个存储单元的晶体管的栅电极分别连接到彼此相邻的字线导体，相邻两个存储单元的晶体管的第二半导体区域连接到相应的两个存储单元的晶体管的第二半导体区域 信息存储电容器。 形成在一个位线导体下方的一系列存储单元对单元结构分别相对于位于一个位线导体的相对侧上相邻的第一和第二位线导体下方的一系列存储单元对单元结构位移地移位， 形成在相邻的第一位线导体下方的存储单元对单元结构的第二信息存储电容器和形成在相邻的第二位线导体下方的存储单元对单元结构的第一信息存储电容器位于与位线连接 形成在一个位线导体下的存储单元对单元结构的导体。