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1.发明授权Nonvolatile memory with blocks and circuitry for selectively protecting the blocks for memory operations 失效具有用于选择性地保护块以用于存储器操作的块和电路的非易失性存储器
公开(公告)号：US5513136A
公开(公告)日：1996-04-30
申请号：US358978
申请日：1994-12-19
摘要： A nonvolatile memory comprises a memory array and a control circuit coupled to the memory array for performing memory operations with respect to the memory array. A storage circuit associated with the memory array is provided for storing a data. When the data is stored in the storage circuit, the memory array is locked from being accessed for the memory operations. A logic circuit is coupled to the control circuit and the storage circuit for preventing the control circuit from accessing the memory array with respect to the memory operations in accordance with the data. The logic circuit prevents the control circuit from accessing the memory array when the storage circuit stores the data. A control input is provided for receiving a control signal. The control signal is applied to the logic circuit and can be in a first voltage state and a second voltage state. When the control signal is in the first voltage state, the logic circuit is enabled to lock the memory array with respect to the memory operations in accordance with the data stored in the storage circuit. When the control signal is in the second voltage state, the logic circuit is disabled to lock the memory array and the memory array is allowed for the memory operations regardless of the data stored in the storage circuit.
摘要翻译： 非易失性存储器包括存储器阵列和耦合到存储器阵列的控制电路，用于执行存储器阵列的存储器操作。 提供与存储器阵列相关联的存储电路用于存储数据。 当数据存储在存储电路中时，存储器阵列被锁定以进行存储器操作。 逻辑电路耦合到控制电路和存储电路，用于根据数据防止控制电路相对于存储器操作访问存储器阵列。 当存储电路存储数据时，逻辑电路防止控制电路访问存储器阵列。 提供控制输入用于接收控制信号。 控制信号被施加到逻辑电路并且可以处于第一电压状态和第二电压状态。 当控制信号处于第一电压状态时，逻辑电路能够根据存储在存储电路中的数据相对于存储器操作锁定存储器阵列。 当控制信号处于第二电压状态时，无论存储在存储电路中的数据如何，逻辑电路被禁用以锁定存储器阵列，并且存储器阵列被允许用于存储器操作。
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2.发明授权Method and device for selectively locking write access to blocks in a memory array using write protect inputs and block enabled status 失效使用写保护输入和块启用状态来选择性地锁定对存储器阵列中的块的写入访问的方法和设备
公开(公告)号：US5592641A
公开(公告)日：1997-01-07
申请号：US85546
申请日：1993-06-30
申请人： Mickey L. Fandrich , Salim B. Fedel , Thomas C. Price , Richard J. Durante , Geoffrey A. Gould , Timothy W. Goodell , Scott M. Doyle
发明人： Mickey L. Fandrich , Salim B. Fedel , Thomas C. Price , Richard J. Durante , Geoffrey A. Gould , Timothy W. Goodell , Scott M. Doyle
摘要： A method and device for selectively enabling and disabling write access to flash blocks in a flash memory device. A lock command locks and unlocks a flash block in a flash array containing a plurality of flash blocks. A block data row decoder selects a block data area of the flash block, and a block status row decoder selects a block status area of the flash block. A lock bit in the block status area is programmed to a first logic state if the lock command specifies a lock flash block operation, or to a second logic state if the lock command specifies a release flash block operation. If a write protect input, read from the write protect pin of the flash memory device, indicates that a write lock is enabled and if a block enabled status bit in a block status register corresponding to the block indicates that the block has the write lock, then the lock bit is read and stored into the block enabled status bit in the block status register corresponding to the block. The write protect input is read again from the write protect pin and if the write protect input indicates that the write lock is enabled, and if the block enabled status bit in the block status register corresponding to the block, as updated, indicates that the block has the write lock, then an error is signaled.
摘要翻译： 一种用于选择性地启用和禁用对闪存设备中的闪存块的写入访问的方法和设备。 锁定命令锁定并解锁包含多个闪存块的闪存阵列中的闪存块。 块数据行解码器选择闪存块的块数据区，块状态行解码器选择闪存块的块状态区。 如果锁定命令指定锁定闪存块操作，则块状态区域中的锁定位被编程为第一逻辑状态，如果锁定命令指定释放闪存块操作，则将其锁定到第二逻辑状态。 如果写保护输入从闪存器件的写保护引脚读取，则指示写锁定被使能，并且如果与该块相对应的块状态寄存器中的块使能状态位指示该块具有写锁定， 则锁定位被读取并存储到与块相对应的块状态寄存器中的块使能状态位。 写保护输入再次从写保护引脚读取，如果写保护输入指示写锁定使能，并且如果块状态寄存器中对应于块更新的块状态寄存器位指示块 有写锁定，然后发出错误信号。
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3.发明授权
公开(公告)号：US5623620A
公开(公告)日：1997-04-22
申请号：US85542
申请日：1993-06-30
CPC分类号： G11C29/48 , G01R31/318516 , G06F12/0246 , G11C11/005 , G11C16/10 , G11C29/26 , G06F11/2273 , G06F2212/7203
摘要： A flash memory device having a page buffer circuit with special testing modes. The page buffer circuit comprises a plane A and a plane B, each comprising a static random access memory array. The page buffer circuit further comprises a mode control circuit that maps the plane A and the plane B as a contiguous extended memory space accessible over a host bus. The page buffer circuit also maps the plane A and the plane B as a control store for a flash array controller of the flash memory device.
摘要翻译： 一种具有特殊测试模式的页面缓冲电路的闪存设备。 页面缓冲电路包括平面A和平面B，每个平面包括静态随机存取存储器阵列。 页面缓冲电路还包括模式控制电路，其将平面A和平面B映射为可通过主机总线访问的连续扩展存储器空间。 页面缓冲电路还将平面A和平面B映射为闪存器件的闪存阵列控制器的控制存储器。
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4.发明授权Circuitry for propagating test mode signals associated with a memory array 失效用于传播与存储器阵列相关联的测试模式信号的电路
公开(公告)号：US5850509A
公开(公告)日：1998-12-15
申请号：US778182
申请日：1997-01-02
摘要： Circuitry for propagating test mode signals associated with a memory array including a plurality of circuits for storing test mode signals, apparatus for selectively providing test mode data to each of the circuits for storing test mode signals, and apparatus for simultaneously activating all of the circuits for storing test mode signals to provide output signals to be used for testing.
摘要翻译： 用于传播与包括用于存储测试模式信号的多个电路的存储器阵列相关联的测试模式信号的电路，用于选择性地向每个用于存储测试模式信号的电路提供测试模式数据的设备，以及用于同时激活所有电路的设备 存储测试模式信号以提供要用于测试的输出信号。
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5.发明授权Apparatus for determining the conditions of programming circuitry used with flash EEPROM memory 失效用于确定与闪存EEPROM存储器一起使用的编程电路条件的装置
公开(公告)号：US5224070A
公开(公告)日：1993-06-29
申请号：US804965
申请日：1991-12-11
IPC分类号： G11C17/00 , G11C16/02 , G11C16/10 , G11C16/34 , G11C29/44 , G11C29/52 , H01L21/822 , H01L27/04
CPC分类号： G11C16/10 , G11C16/3436 , G11C29/44 , G11C29/52 , G11C2216/20
摘要： A circuit which monitors the internal state of flash memory array programming circuitry and conveys that state to circuitry external to the flash memory array so that external circuitry need not delay during any period in which a programming operation is taking place within the flash memory array.
摘要翻译： 监视闪存阵列编程电路的内部状态并将该状态传送到闪速存储器阵列外部的电路的电路，使得外部电路不需要在闪存阵列内发生编程操作的任何周期期间延迟。
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6.发明授权
公开(公告)号：US5835927A
公开(公告)日：1998-11-10
申请号：US719583
申请日：1996-09-25
IPC分类号： G01R31/3185 , G06F11/22 , G06F12/02 , G11C11/00 , G11C16/10 , G11C29/26 , G11C29/48 , G06F12/00
CPC分类号： G11C29/48 , G01R31/318516 , G06F12/0246 , G11C11/005 , G11C16/10 , G11C29/26 , G06F11/2273 , G06F2212/7203
摘要： A flash memory device having a page buffer circuit with special testing modes. The page buffer circuit comprises a plane A and a plane B, each comprising a static random access memory array. The page buffer circuit further comprises a mode control circuit that maps the plane A and the plane B as a contiguous extended memory space accessible over a host bus. The page buffer circuit also maps the plane A and the plane B as a control store for a flash array controller of the flash memory device.
摘要翻译： 一种具有特殊测试模式的页面缓冲电路的闪存设备。 页面缓冲电路包括平面A和平面B，每个平面包括静态随机存取存储器阵列。 页面缓冲电路还包括模式控制电路，其将平面A和平面B映射为可通过主机总线访问的连续扩展存储器空间。 页面缓冲电路还将平面A和平面B映射为闪存器件的闪存阵列控制器的控制存储器。
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7.发明授权Circuitry and method for selectively protecting the integrity of data stored within a range of addresses within a non-volatile semiconductor memory 失效用于选择性地保护存储在非易失性半导体存储器内的地址范围内的数据的完整性的电路和方法
公开(公告)号：US5546561A
公开(公告)日：1996-08-13
申请号：US372891
申请日：1995-01-13
CPC分类号： G11C16/3445 , G11C16/102 , G11C16/3436 , G11C16/3459
摘要： A circuit for selectively protecting data stored within a range of addresses from programming and erasing. The circuit includes a circuit for generating an active lock signal. The circuit generates an active lock signal when a protect signal is active and an address signal represents an address within the protected range. Both erasure and programming are prevented while the lock signal is active. Programming and erasure of protected data is permitted while the lock signal is inactive. A method for selectively protecting data within a range of addresses on a non-volatile semiconductor memory from programming or erasure is also described.
摘要翻译： 用于选择性地保护存储在地址范围内的数据不被编程和擦除的电路。 该电路包括用于产生主动锁定信号的电路。 当保护信号有效并且地址信号表示受保护范围内的地址时，该电路产生有效的锁定信号。 当锁定信号有效时，可以防止擦除和编程。 当锁定信号无效时，允许对受保护数据进行编程和擦除。 还描述了一种用于选择性地保护非易失性半导体存储器上的地址范围内的数据不被编程或擦除的方法。
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8.发明授权Circuitry and method for programming and erasing a non-volatile semiconductor memory 失效用于编程和擦除非易失性半导体存储器的电路和方法
公开(公告)号：US5448712A
公开(公告)日：1995-09-05
申请号：US201044
申请日：1994-02-24
CPC分类号： G11C16/3445 , G11C16/102 , G11C16/3436 , G11C16/3459
摘要： Erase control circuitry for erasing a flash memory array. The erase control circuitry resides on the same substrate as the flash memory array, along with a command state machine. The command state machine recognizes and externally generated erase command applied to the terminals and generates an active erase control signal, to which the erase control circuitry responds. The erase control circuitry includes precondition pulse application circuitry, erase pulse application circuitry and erase verification circuitry. The precondition pulse application circuitry preconditions the array by programming each bit in the flash memory to a threshold voltage level representative of a programmed state. The erase pulse application circuitry applies a single erase pulse at a time to the flash memory array to erase the flash array by bringing the threshold voltage level of each cell in the array to a level representative of an erased state. The erase verification circuitry verifies the erasure of the flash memory array on a byte by byte basis. If the byte currently being verified has been erased; the erase verification circuitry brings a match signal to an active level. The erase control circuitry determines whether additional erase pulses should be applied to the flash array based upon the match signal and the number of erase pulses previously applied to the flash array described is program control circuitry and methods of programming and erasing a flash memory array in response to two step command sequences.
摘要翻译： 擦除控制电路以擦除闪存阵列。 擦除控制电路与命令状态机一起位于与闪存阵列相同的衬底上。 命令状态机识别并向外部产生的擦除命令，并产生一个有效的擦除控制信号，擦除控制电路对其进行响应。 擦除控制电路包括预处理脉冲应用电路，擦除脉冲应用电路和擦除验证电路。 预处理脉冲应用电路通过将闪速存储器中的每个位编程为表示编程状态的阈值电压电平来预先调整阵列。 擦除脉冲施加电路通过将阵列中的每个单元的阈值电压电平提升到表示擦除状态的电平，将一次擦除脉冲一次施加到闪存阵列以擦除闪存阵列。 擦除验证电路以逐个字节为基础来验证闪速存储器阵列的擦除。 如果当前正在验证的字节已被擦除; 擦除验证电路将匹配信号带到活动电平。 擦除控制电路基于匹配信号确定是否应该向闪存阵列施加额外的擦除脉冲，并且先前施加到所述闪存阵列的擦除脉冲的数量是程序控制电路以及响应于编程和擦除闪存阵列的方法 到两步命令序列。
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公开(公告)号：US5463757A
公开(公告)日：1995-10-31
申请号：US185449
申请日：1994-01-21
CPC分类号： G11C16/32 , G11C16/10 , G11C2216/20
摘要： A command state machine for control circuitry associated with a memory array which control circuitry includes apparatus for programming and erasing the memory array including first state machine logic apparatus for providing control signals for reading the memory array and for initiating operations of the apparatus for programming and erasing the memory array in response to commands, and second state machine logic apparatus for controlling information derived from the memory array, the first and second state machine logic apparatus being adapted to assume predetermined states in response to any invalid command which have no adverse affect on the memory array or the control circuitry.
摘要翻译： 一种用于与存储器阵列相关联的控制电路的命令状态机，所述控制电路包括用于编程和擦除存储器阵列的装置，所述装置包括用于提供用于读取存储器阵列的控制信号的第一状态机逻辑装置，以及用于启动用于编程和擦除的装置的操作 所述存储器阵列响应于命令，以及用于控制从所述存储器阵列导出的信息的第二状态机逻辑装置，所述第一和第二状态机逻辑装置适于响应于对所述存储阵列没有不利影响的任何无效命令而呈现预定状态 存储器阵列或控制电路。
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10.发明授权Circuitry and method for suspending the automated erasure of a non-volatile semiconductor memory 失效用于暂停非易失性半导体存储器的自动擦除的电路和方法
公开(公告)号：US5355464A
公开(公告)日：1994-10-11
申请号：US655650
申请日：1991-02-11
CPC分类号： G11C16/16 , G11C2216/20
摘要： Circuitry for suspending an automated sequence for a nonvolatile semiconductor memory is described. The circuitry and memory reside on the same substrate. The circuitry includes a circuit for suspending erasure at a predetermined state of the erase sequence when a suspend signal is active and a circuit for resuming erasure at a predetermined state of the erase sequence when the suspend signal goes inactive. A method for suspending automated erasure sequence of a non-volatile semiconductor memory is also described. A suspend signal is received and erasure is suspended after a first erasure step of the erase sequence if suspend signal is active. Erasure resumes at a second erasure step of the erase sequence when the suspend signal goes inactive.
摘要翻译： 描述用于暂停用于非易失性半导体存储器的自动化序列的电路。 电路和存储器位于相同的衬底上。 该电路包括一个电路，用于当暂停信号有效时，在擦除序列的预定状态下暂停擦除，以及当暂停信号变为不活动时，在擦除序列的预定状态下恢复擦除的电路。 还描述了一种用于暂停非易失性半导体存储器的自动擦除序列的方法。 如果暂停信号有效，则在擦除序列的第一擦除步骤之后，接收暂停信号并且擦除被暂停。 当挂起信号变为非活动状态时，擦除顺序的第二擦除步骤恢复擦除。
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