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公开(公告)号：US20160098223A1
公开(公告)日：2016-04-07
申请号：US14967934
申请日：2015-12-14
Applicant: Micron Technology, Inc.
Inventor： Federico Tiziani , Giovanni Campardo , Massimo Iaculo , Claudio Giaccio , Manuela Scognamiglio , Danilo Caraccio , Ornella Vitale , Antonino Pollio
CPC classification number: G06F3/0625 , G06F1/3275 , G06F3/0634 , G06F3/0659 , G06F3/0679 , G06F11/10 , G06F11/1044 , G06F11/1068 , G06F11/1072 , G06F12/0246 , G06F13/1668 , G11C29/52 , Y02D10/14
Abstract: A single virtualized ECC NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack.
Abstract translation: 单个虚拟化ECC NAND控制器执行ECC算法并管理NAND闪存堆栈。 虚拟化ECC NAND控制器允许主机处理器作为单个NAND芯片驱动闪存器件堆叠，同时控制器将数据重定向到堆栈中选择的NAND存储器件。
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公开(公告)号：US20140351675A1
公开(公告)日：2014-11-27
申请号：US14456559
申请日：2014-08-11
Applicant: Micron Technology, Inc.
Inventor： Federico Tiziani , Giovanni Campardo , Massimo Iaculo , Claudio Giaccio , Manuela Scognamiglio , Danilo Caraccio , Ornella Vitale , Antonino Pollio
CPC classification number: G06F3/0625 , G06F1/3275 , G06F3/0634 , G06F3/0659 , G06F3/0679 , G06F11/10 , G06F11/1044 , G06F11/1068 , G06F11/1072 , G06F12/0246 , G06F13/1668 , G11C29/52 , Y02D10/14
Abstract: In various embodiments, a single virtualized error correcting code (ECC) NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack. In various embodiments, a controller manages a plurality of NAND memory devices. The controller provides power to a select one of the plurality of NAND memory devices at a time to conserve overall power consumption of the storage system.
Abstract translation: 在各种实施例中，单个虚拟化纠错码（ECC）NAND控制器执行ECC算法并管理NAND闪存堆栈。 虚拟化ECC NAND控制器允许主机处理器作为单个NAND芯片驱动闪存器件堆叠，同时控制器将数据重定向到堆栈中选择的NAND存储器件。 在各种实施例中，控制器管理多个NAND存储器件。 控制器一次为多个NAND存储器件中的一个选择一个供电，以节省存储系统的整体功耗。
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公开(公告)号：US09213603B2
公开(公告)日：2015-12-15
申请号：US14456559
申请日：2014-08-11
Applicant: Micron Technology, Inc.
Inventor： Federico Tiziani , Giovanni Campardo , Massimo Iaculo , Claudio Giaccio , Manuela Scognamiglio , Danilo Caraccio , Ornella Vitale , Antonino Pollio
CPC classification number: G06F3/0625 , G06F1/3275 , G06F3/0634 , G06F3/0659 , G06F3/0679 , G06F11/10 , G06F11/1044 , G06F11/1068 , G06F11/1072 , G06F12/0246 , G06F13/1668 , G11C29/52 , Y02D10/14
Abstract: In various embodiments, a single virtualized error correcting code (ECC) NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack. In various embodiments, a controller manages a plurality of NAND memory devices. The controller provides power to a select one of the plurality of NAND memory devices at a time to conserve overall power consumption of the storage system.
Abstract translation: 在各种实施例中，单个虚拟化纠错码（ECC）NAND控制器执行ECC算法并管理NAND闪存堆栈。 虚拟化ECC NAND控制器允许主机处理器作为单个NAND芯片驱动闪存器件堆叠，同时控制器将数据重定向到堆栈中选择的NAND存储器件。 在各种实施例中，控制器管理多个NAND存储器件。 控制器一次为多个NAND存储器件中的一个选择一个供电，以节省存储系统的整体功耗。
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公开(公告)号：US08984370B2
公开(公告)日：2015-03-17
申请号：US13907524
申请日：2013-05-31
Applicant: Micron Technology, Inc.
Inventor： Giovanni Campardo , Stefano Corno , Gian Pietro Vanalli , Manuela Scognamiglio , Danilo Caraccio , Federico Tiziani , Massimiliano Magni , Andrea Ghilardelli
CPC classification number: G11C29/42 , G06F11/1048 , G11C2029/0411
Abstract: A system and method are disclosed in which a first non-volatile memory includes blocks that store data, and a second memory that stores error correction information related to the blocks storing the data. The first memory and the second memory are of different types.
Abstract translation: 公开了一种系统和方法，其中第一非易失性存储器包括存储数据的块和存储与存储数据的块相关的纠错信息的第二存储器。 第一个内存和第二个内存是不同的类型。
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公开(公告)号：US20130332800A1
公开(公告)日：2013-12-12
申请号：US13907524
申请日：2013-05-31
Applicant: Micron Technology, Inc.
Inventor： Giovanni Campardo , Stefano Corno , Gian Pietro Vanalli , Manuela Scognamiglio , Danilo Caraccio , Federico Tiziani , Massimiliano Magni , Andrea Ghilardelli
IPC: G11C29/42
CPC classification number: G11C29/42 , G06F11/1048 , G11C2029/0411
Abstract: A system and method are disclosed in which a first non-volatile memory includes blocks that store data, and a second memory that stores error correction information related to the blocks storing the data. The first memory and the second memory are of different types.
Abstract translation: 公开了一种系统和方法，其中第一非易失性存储器包括存储数据的块和存储与存储数据的块相关的纠错信息的第二存储器。 第一个内存和第二个内存是不同的类型。
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Patent Agency Ranking
公开(公告)号：US20130268825A1
公开(公告)日：2013-10-10
申请号：US13907669
申请日：2013-05-31
Applicant: Micron Technology, Inc.
Inventor： Giovanni Campardo , Stefano Corno , Gian Pietro Vanalli , Manuela Scognamiglio , Danilo Caraccio , Frederico Tiziani , Massimiliano Magni , Andrea Ghilardelli
IPC: G11C29/42
CPC classification number: G11C29/42 , G06F11/1048 , G11C2029/0411
Abstract: A method and system are disclosed in which a first non-volatile memory includes blocks that store data, and a second memory that stores overhead information related to the blocks storing the data. The amount of the second memory storing the overhead information related to the at least one block of the plurality of blocks is varied.
Abstract translation: 公开了一种方法和系统，其中第一非易失性存储器包括存储数据的块和存储与存储数据的块有关的开销信息的第二存储器。 存储与多个块的至少一个块相关的开销信息的第二存储器的量是变化的。
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公开(公告)号：US09971536B2
公开(公告)日：2018-05-15
申请号：US15431457
申请日：2017-02-13
Applicant: Micron Technology, Inc.
Inventor： Federico Tiziani , Giovanni Campardo , Massimo Iaculo , Claudio Giaccio , Manuela Scognamiglio , Danilo Caraccio , Ornella Vitale , Antonino Pollio
CPC classification number: G06F3/0625 , G06F1/3275 , G06F3/0634 , G06F3/0659 , G06F3/0679 , G06F11/10 , G06F11/1044 , G06F11/1068 , G06F11/1072 , G06F12/0246 , G06F13/1668 , G11C29/52 , Y02D10/14
Abstract: Various embodiments disclose a controller to manage memory devices. In an exemplary method, signals are exchanged with a host processor to allow the host processor to communicate with multiple memory devices in a memory stack as a single device, regardless of an actual number of memory devices within the memory stack. Power is provided to a single one of the multiple memory devices in the memory stack at a time to reduce power consumption. Other methods, apparatuses, and devices are also disclosed.
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公开(公告)号：US20170160973A1
公开(公告)日：2017-06-08
申请号：US15431457
申请日：2017-02-13
Applicant: Micron Technology, Inc.
Inventor： Federico Tiziani , Giovanni Campardo , Massimo Iaculo , Claudio Giaccio , Manuela Scognamiglio , Danilo Caraccio , Ornella Vitale , Antonino Pollio
CPC classification number: G06F3/0625 , G06F1/3275 , G06F3/0634 , G06F3/0659 , G06F3/0679 , G06F11/10 , G06F11/1044 , G06F11/1068 , G06F11/1072 , G06F12/0246 , G06F13/1668 , G11C29/52 , Y02D10/14
Abstract: A single virtualized ECC NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack.
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公开(公告)号：US09569129B2
公开(公告)日：2017-02-14
申请号：US14967934
申请日：2015-12-14
Applicant: Micron Technology, Inc.
Inventor： Federico Tiziani , Giovanni Campardo , Massimo Iaculo , Claudio Giaccio , Manuela Scognamiglio , Danilo Caraccio , Ornella Vitale , Antonino Pollio
CPC classification number: G06F3/0625 , G06F1/3275 , G06F3/0634 , G06F3/0659 , G06F3/0679 , G06F11/10 , G06F11/1044 , G06F11/1068 , G06F11/1072 , G06F12/0246 , G06F13/1668 , G11C29/52 , Y02D10/14
Abstract: Various embodiments disclose a controller to manage memory devices. In an exemplary method, signals are exchanged with a host processor to allow the host processor to communicate with a plurality of memory devices in a memory stack as a single device, regardless of an actual number of memory devices within the memory stack. Power is provided to a single one of the plurality of the memory devices in the memory stack at a time to reduce power consumption. Other methods, apparatuses, and devices are also disclosed.
Abstract translation: 各种实施例公开了一种用于管理存储器件的控制器。 在示例性方法中，信号与主处理器交换，以允许主机处理器作为单个设备与存储器堆叠中的多个存储器件通信，而不管存储器堆栈内的实际数量的存储器件。 一次将功率提供给存储器堆叠中的多个存储器件中的单个存储器件，以降低功耗。 还公开了其它方法，装置和装置。
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公开(公告)号：US08880979B2
公开(公告)日：2014-11-04
申请号：US13907669
申请日：2013-05-31
Applicant: Micron Technology, Inc.
Inventor： Giovanni Campardo , Stefano Corno , Gian Pietro Vanalli , Manuela Scognamiglio , Danilo Caraccio , Federico Tiziani , Massimiliano Magni , Andrea Ghilardelli
CPC classification number: G11C29/42 , G06F11/1048 , G11C2029/0411
Abstract: A method and system are disclosed in which a first non-volatile memory includes blocks that store data, and a second memory that stores overhead information related to the blocks storing the data. The amount of the second memory storing the overhead information related to the at least one block of the plurality of blocks is varied.
Abstract translation: 公开了一种方法和系统，其中第一非易失性存储器包括存储数据的块和存储与存储数据的块有关的开销信息的第二存储器。 存储与多个块的至少一个块相关的开销信息的第二存储器的量是变化的。
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