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    Programmable memory timing
    1.
    发明授权
    Programmable memory timing 有权

    公开(公告)号：US11894099B2

    公开(公告)日：2024-02-06

    申请号：US17562560

    申请日：2021-12-27

    Applicant: Micron Technology, Inc.

    Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  Timothy M. Hollis ,  Dong Soon Lim

    IPC: G06F13/16 ,  G11C7/22 ,  G11C7/10 ,  G06F3/06 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/10

    CPC classification number: G11C7/1087 ,  G06F3/0679 ,  G06F13/1689 ,  G11C7/22 ,  G11C11/4093 ,  G11C29/022 ,  G11C29/028 ,  G11C29/10

    Abstract: Described apparatuses and methods enable communication between a host device and a memory device to establish relative delays between different data lines. If data signals propagate along a bus with the same timing, simultaneous switching output (SSO) and crosstalk can adversely impact channel timing budget parameters. An example system includes an interconnect having multiple data lines that couple the host device to the memory device. In example operations, the host device can transmit to the memory device a command indicative of a phase offset between two or more data lines of the multiple data lines. The memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets between data lines. The host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. Lengths of the offsets can vary. Further, a system can activate the phase offsets based on frequency.

    SEMICONDUCTOR PACKAGES AND ASSOCIATED METHODS WITH ANTENNAS AND EMI ISOLATION SHIELDS
    3.
    发明申请
    SEMICONDUCTOR PACKAGES AND ASSOCIATED METHODS WITH ANTENNAS AND EMI ISOLATION SHIELDS 有权

    公开(公告)号：US20220068837A1

    公开(公告)日：2022-03-03

    申请号：US17524473

    申请日：2021-11-11

    Applicant: Micron Technology, Inc.

    Inventor： Owen R. Fay ,  Dong Soon Lim ,  Randon K. Richards ,  Aparna U. Limaye

    IPC: H01L23/552 ,  H01L23/66 ,  H01L23/31 ,  H01L21/56 ,  H01Q1/22

    Abstract: Semiconductor devices with antennas and electromagnetic interference (EMI) shielding, and associated systems and methods, are described herein. In one embodiment, a semiconductor device includes a semiconductor die coupled to a package substrate. An antenna structure is disposed over and/or adjacent the semiconductor die. An electromagnetic interference (EMI) shield is disposed between the semiconductor die and the antenna structure to shield at least the semiconductor die from electromagnetic radiation generated by the antenna structure and/or to shield the antenna structure from interference generated by the semiconductor die. A first dielectric material and/or a thermal interface material can be positioned between the semiconductor die and the EMI shield, and a second dielectric material can be positioned between the EMI shield and the antenna structure. In some embodiments, the semiconductor device includes a package molding over at least a portion of the antenna, the EMI shield, and/or the second dielectric material.

    Programmable memory timing
    4.
    发明授权
    Programmable memory timing 有权

    公开(公告)号：US12176061B2

    公开(公告)日：2024-12-24

    申请号：US18420404

    申请日：2024-01-23

    Applicant: Micron Technology, Inc.

    Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  Timothy M. Hollis ,  Dong Soon Lim

    IPC: G11C7/10 ,  G06F3/06 ,  G06F13/16 ,  G11C7/22 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/10

    Abstract: Described apparatuses and methods enable communication between a host device and a memory device to establish relative delays between different data lines. If data signals propagate along a bus with the same timing, simultaneous switching output (SSO) and crosstalk can adversely impact channel timing budget parameters. An example system includes an interconnect having multiple data lines that couple the host device to the memory device. In example operations, the host device can transmit to the memory device a command indicative of a phase offset between two or more data lines of the multiple data lines. The memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets between data lines. The host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. Lengths of the offsets can vary. Further, a system can activate the phase offsets based on frequency.

    Semiconductor packages and associated methods with antennas and EMI isolation shields
    8.
    发明授权
    Semiconductor packages and associated methods with antennas and EMI isolation shields 有权

    公开(公告)号：US11177222B2

    公开(公告)日：2021-11-16

    申请号：US16524989

    申请日：2019-07-29

    Applicant: Micron Technology, Inc.

    Inventor： Owen R. Fay ,  Dong Soon Lim ,  Randon K. Richards ,  Aparna U. Limaye

    IPC: H01L23/58 ,  H01L23/552 ,  H01L23/66 ,  H01L23/31 ,  H01L21/56 ,  H01Q1/22

    Abstract: Semiconductor devices with antennas and electromagnetic interference (EMI) shielding, and associated systems and methods, are described herein. In one embodiment, a semiconductor device includes a semiconductor die coupled to a package substrate. An antenna structure is disposed over and/or adjacent the semiconductor die. An electromagnetic interference (EMI) shield is disposed between the semiconductor die and the antenna structure to shield at least the semiconductor die from electromagnetic radiation generated by the antenna structure and/or to shield the antenna structure from interference generated by the semiconductor die. A first dielectric material and/or a thermal interface material can be positioned between the semiconductor die and the EMI shield, and a second dielectric material can be positioned between the EMI shield and the antenna structure. In some embodiments, the semiconductor device includes a package molding over at least a portion of the antenna, the EMI shield, and/or the second dielectric material.

    Programmable Memory Timing
    9.
    发明公开
    Programmable Memory Timing 审中-公开

    公开(公告)号：US20240161796A1

    公开(公告)日：2024-05-16

    申请号：US18420404

    申请日：2024-01-23

    Applicant: Micron Technology, Inc.

    Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  Timothy M. Hollis ,  Dong Soon Lim

    IPC: G11C7/10 ,  G06F3/06 ,  G06F13/16 ,  G11C7/22 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/10

    CPC classification number: G11C7/1087 ,  G06F3/0679 ,  G06F13/1689 ,  G11C7/22 ,  G11C11/4093 ,  G11C29/022 ,  G11C29/028 ,  G11C29/10

    Abstract: Described apparatuses and methods enable communication between a host device and a memory device to establish relative delays between different data lines. If data signals propagate along a bus with the same timing, simultaneous switching output (SSO) and crosstalk can adversely impact channel timing budget parameters. An example system includes an interconnect having multiple data lines that couple the host device to the memory device. In example operations, the host device can transmit to the memory device a command indicative of a phase offset between two or more data lines of the multiple data lines. The memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets between data lines. The host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. Lengths of the offsets can vary. Further, a system can activate the phase offsets based on frequency.

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