公开(公告)号：US20240237364A1

公开(公告)日：2024-07-11

申请号：US18417830

申请日：2024-01-19

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro ,  Stephen W. Russell ,  Stephen H. Tang

IPC: H10B99/00 ,  G11C8/10 ,  G11C8/12 ,  H01L21/027 ,  H01L21/311 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B53/20 ,  H10B53/40 ,  H10B63/00

CPC classification number: H10B99/00 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/41741 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78642 ,  H01L29/78696 ,  G11C8/10 ,  G11C8/12 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/31144 ,  H10B53/20 ,  H10B53/40 ,  H10B63/84

Abstract: Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

公开(公告)号：US10950663B2

公开(公告)日：2021-03-16

申请号：US15961547

申请日：2018-04-24

Applicant: Micron Technology, inc.

Inventor： Hernan A. Castro ,  Stephen H. Tang ,  Stephen W. Russell

IPC: H01L27/24 ,  H01L27/11514 ,  H01L45/00

Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.

公开(公告)号：US10854286B2

公开(公告)日：2020-12-01

申请号：US16218478

申请日：2018-12-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Stephen H. Tang

IPC: G11C8/00 ,  G11C13/00 ,  G11C8/08 ,  G11C8/10

Abstract: Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. The first select line is configured to provide a first voltage, the second select line is configured to provide a second voltage, and the polarity line is configured to provide a polarity signal. The address decoder circuit is configured to receive address information and further configured to couple the access line to the first select line responsive to the address information having a combination of logic levels and the polarity signal having a first logic level and further configured to couple the access line to the second select line responsive to the address information having the combination of logic levels and the polarity signal having a second logic level.

公开(公告)号：US20190326357A1

公开(公告)日：2019-10-24

申请号：US15961547

申请日：2018-04-24

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro ,  Stephen H. Tang ,  Stephen W. Russell

IPC: H01L27/24 ,  H01L27/11514

Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.

公开(公告)号：US10163501B2

公开(公告)日：2018-12-25

申请号：US15684784

申请日：2017-08-23

Applicant: Micron Technology, Inc.

Inventor： Stephen H. Tang

IPC: G11C8/00 ,  G11C13/00 ,  G11C8/08 ,  G11C8/10

Abstract: Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. The first select line is configured to provide a first voltage, the second select line is configured to provide a second voltage, and the polarity line is configured to provide a polarity signal. The address decoder circuit is configured to receive address information and further configured to couple the access line to the first select line responsive to the address information having a combination of logic levels and the polarity signal having a first logic level and further configured to couple the access line to the second select line responsive to the address information having the combination of logic levels and the polarity signal having a second logic level.

公开(公告)号：US20170352416A1

公开(公告)日：2017-12-07

申请号：US15684784

申请日：2017-08-23

Applicant: Micron Technology, Inc.

Inventor： Stephen H. Tang

IPC: G11C13/00 ,  G11C8/08 ,  G11C8/10

CPC classification number: G11C13/0023 ,  G11C8/08 ,  G11C8/10 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069

Abstract: Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. The first select line is configured to provide a first voltage, the second select line is configured to provide a second voltage, and the polarity line is configured to provide a polarity signal. The address decoder circuit is configured to receive address information and further configured to couple the access line to the first select line responsive to the address information having a combination of logic levels and the polarity signal having a first logic level and further configured to couple the access line to the second select line responsive to the address information having the combination of logic levels and the polarity signal having a second logic level.

公开(公告)号：US20160307626A1

公开(公告)日：2016-10-20

申请号：US15197539

申请日：2016-06-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Stephen H. Tang

IPC: G11C13/00

CPC classification number: G11C13/0023 ,  G11C8/08 ,  G11C8/10 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069

Abstract: Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. The first select line is configured to provide a first voltage, the second select line is configured to provide a second voltage, and the polarity line is configured to provide a polarity signal. The address decoder circuit is configured to receive address information and further configured to couple the access line to the first select line responsive to the address information having a combination of logic levels and the polarity signal having a first logic level and further configured to couple the access line to the second select line responsive to the address information having the combination of logic levels and the polarity signal having a second logic level.

公开(公告)号：US20150179253A1

公开(公告)日：2015-06-25

申请号：US14139493

申请日：2013-12-23

Applicant: Micron Technology, Inc.

Inventor： Stephen H. Tang

IPC: G11C13/00

CPC classification number: G11C13/0023 ,  G11C8/08 ,  G11C8/10 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069

Abstract: Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. The first select line is configured to provide a first voltage, the second select line is configured to provide a second voltage, and the polarity line is configured to provide a polarity signal. The address decoder circuit is configured to receive address information and further configured to couple the access line to the first select line responsive to the address information having a combination of logic levels and the polarity signal having a first logic level and further configured to couple the access line to the second select line responsive to the address information having the combination of logic levels and the polarity signal having a second logic level.

Abstract translation: 公开了用于解码用于选择存储器中的存取线的存储器地址的装置，存储器和方法。 示例性设备包括耦合到第一和第二选择线，极性线和接入线的地址解码器电路。 第一选择线被配置为提供第一电压，第二选择线被配置为提供第二电压，并且极性线被配置为提供极性信号。 地址解码器电路被配置为接收地址信息，并且还被配置为响应于具有逻辑电平的组合的地址信息和具有第一逻辑电平的极性信号而将访问线耦合到第一选择线，并且还被配置为耦合访问 响应于具有逻辑电平的组合的地址信息和具有第二逻辑电平的极性信号，线路到第二选择线。

公开(公告)号：US12087758B2

公开(公告)日：2024-09-10

申请号：US16905363

申请日：2020-06-18

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro ,  Stephen W. Russell ,  Stephen H. Tang

IPC: H01L27/02 ,  H01L21/768 ,  H01L27/04 ,  H05K1/11 ,  H05K3/00 ,  H05K3/22 ,  H10B99/00 ,  H10B63/00

CPC classification number: H01L27/0207 ,  H01L21/76816 ,  H01L27/04 ,  H05K1/116 ,  H05K3/0094 ,  H05K3/225 ,  H10B99/00 ,  H10B63/84

Abstract: Methods, systems, and devices for buried lines and related fabrication techniques are described. An electronic device (e.g., an integrated circuit) may include multiple buried lines at multiple layers of a stack. For example, a first layer of the stack may include multiple buried lines formed based on a pattern of vias formed at an upper layer of the stack. The pattern of vias may be formed in a wide variety of spatial configurations, and may allow for conductive material to be deposited at a buried target layer. In some cases, buried lines may be formed at multiple layers of the stack concurrently.

公开(公告)号：US20240292632A1

公开(公告)日：2024-08-29

申请号：US18657259

申请日：2024-05-07

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro ,  Stephen H. Tang ,  Stephen W. Russell

IPC: H10B63/00 ,  H10B53/20 ,  H10N70/20

CPC classification number: H10B63/845 ,  H10B53/20 ,  H10B63/20 ,  H10B63/22 ,  H10B63/24 ,  H10B63/80 ,  H10B63/84 ,  H10N70/235 ,  H10N70/245

Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.